Electricity: measuring and testing – Fault detecting in electric circuits and of electric components – Of individual circuit component or element
Reexamination Certificate
2001-06-29
2004-04-06
Pert, Evan (Department: 2829)
Electricity: measuring and testing
Fault detecting in electric circuits and of electric components
Of individual circuit component or element
Reexamination Certificate
active
06717429
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates generally to integrated circuits and, more particularly, to systems and methods for testing integrated circuits.
BACKGROUND OF THE INVENTION
As transistor geometry continues to shrink, more and more functional circuitry may be embedded within integrated circuits (ICs). This trend is beneficial for the electronics industry since it enables development of smaller, lower power electronic consumer products, such as cell phones and hand held computers. However, as IC circuit density increases, the testing of ICs becomes more complex and costly for the IC manufacturers. Reducing the cost of manufacturing ICs is a primary goal for every IC manufacturer By reducing IC manufacturing cost, an IC manufacturer can advantageously cost-differentiate its IC products from other IC manufacturers.
FIG. 1A
illustrates a semiconductor wafer
101
comprising multiple die
102
circuits.
FIG. 1B
illustrates one of the die circuits
101
on wafer
101
. The die contains core circuitry
103
, which provides the functionality of the die, and pad locations
104
for providing contacts for accessing the core circuitry.
FIG. 1C
illustrates a conventional test arrangement for contacting and testing a single die
102
of wafer
101
. The test arrangement includes a tester
105
, a single die probe mechanism
109
, and a die
102
to be tested. Tester
105
comprises a controller
106
, stimulus circuitry
108
, and response circuitry
107
. Controller
106
regulates the stimulus circuitry
108
via interface
117
to output test stimulus signals to die
102
via stimulus bus
111
. Controller
106
regulates the response circuitry
107
via interface
118
to receive test response signals from die
102
via response bus
110
. Probe mechanism
109
comprises the stimulus bus
111
and response bus
110
connection channels between tester
105
and die
102
. The probe mechanism contacts the input
115
and output
116
die pads via small probe needles
112
. While only a pair of input and output probe needles
112
are shown in this simple illustration, it is understood that all die input and output pads will be similarly contacted by the probe mechanism
109
using additional probe needles
112
. The input pads
115
transfer stimulus signals to core
103
via input buffers
113
, and the output pads
116
transfer test response signals from core
103
via output buffers
114
. The testing of the die
102
in
FIG. 1C
occurs through the process of inputting stimulus signals to the die and receiving response signals from the die.
FIG. 2
illustrates in more detail the stimulus
108
and response
107
circuitry of tester
105
. Stimulus circuitry
108
typically comprises a large stimulus data memory
201
for storing the stimulus data to be applied to the die. Controller
106
controls the loading of the stimulus data memory
201
from a source, such as a hard disk, prior to testing, and then controls the stimulus data memory to output the loaded stimulus data to the die during test, via stimulus bus
111
. Response circuitry
107
typically comprises a large mask and expected data memory
203
, a comparator
204
, and a fail flag memory
202
. The mask and expected data memory
203
stores mask and expected data to be used by the comparator
204
to determine if the response data from the die passes or fails.
During test, the comparator
204
inputs response signals from the die via response bus
110
, and mask (M) and expected (E) data signals from memory
203
via mask and expected data buses
206
and
207
. If not masked, by mask signal input from memory
203
, a given response signal from the die is compared against a corresponding expected data signal from memory
203
. If masked, by mask signal input from memory
203
, a given response signal from the die is not compared against an expected data signal from memory
203
. If a non-masked response signal matches the expected signal, the compare test passes for that signal. However, if a non-masked response signal does not match the expected signal, the compare test fails for that signal and the comparator outputs a corresponding fail signal on bus
205
to fail flag memory
202
. At the end of test, the controller
106
reads the fail flag memory to determine if the die test passed or failed. Alternately, and preferably in a production test mode, the single die test may be halted immediately upon the controller receiving a compare fail indication from the fail flag memory
202
, via the interface
118
between controller
106
and response circuitry
107
, to reduce wafer test time. At the end of the single die test, the probe mechanism is relocated to make contact to another single die
102
of wafer
101
and the single die test is repeated. The wafer test completes after all die
102
of wafer
101
have each been contacted and tested as described above.
FIG. 3
illustrates a conventional test arrangement for simultaneously contacting and testing multiple die
102
of wafer
101
. The test arrangement includes tester
105
, multiple die probe mechanism
301
, and a multiple die
1
-N
102
to be tested. The difference between the single and multiple die test arrangements of
FIGS. 2 and 3
is in the use of the multiple die probe mechanism
301
. As seen in
FIG. 3
, the connection between probe mechanism
301
and tester
105
is as previously described. However, the connection between probe mechanism
301
and die
1
-N is different. Each stimulus bus signal from the tester uniquely probes common pad inputs on each die
1
-N. For example, the stimulus
1
(S
1
) signal from the stimulus bus probes all common input pads
303
of all die
1
-N via connection
302
. While not shown, stimulus
2
-N (S
2
-N) signals from the stimulus bus would each similarly probe all other common input pads of all die
1
-N. This allows the stimulus bus signals to simultaneously input the same stimulus to all die
1
-N during the test.
As seen in
FIG. 3
, the die response connection of probe mechanism
301
is different from the above described die stimulus connection. Whereas each common input pad
303
of die
1
-N share a single stimulus signal connection
302
, each common output pad
304
requires use of a dedicated response signal connection. For example, output pad
304
of die
1
uses a response signal connection
305
, output pad
304
of die
2
uses a response signal connection
306
, output pad
304
of die
3
uses a response signal connection
307
, and output pad
304
of die N uses a response signal connection
308
. All other output pads of die
1
-N would similarly use a dedicated response signal connection. All dedicated response signal connections are channeled into the response bus to tester
105
, as seen in FIG.
3
. During test, the tester outputs stimulus to all die
1
-N and receives response outputs from all die
1
-N. The test time of testing multiple die in
FIG. 3
is the same as testing single die in FIG.
2
. The test operates in the masked
on-masked compare mode as described in
FIGS. 1C and 2
. When testing multiple die simultaneously, as opposed to testing a single die, a production test preferably runs to completion even though an early compare may occur on one or more of the die being tested. This is done because typically most of the die will pass the production test and aborting the multiple die production test on a failure indication would actually increase the test time, since the test would need to be re-run later to complete the testing of the passing die.
The limitation of the multiple die test arrangement in
FIG. 3
lies in the number of dedicated response inputs
305
-
308
the tester
105
can accept on its response bus. For example, if the tester can accept 300 response input signals and each die has 100 output pads, the multiple die test arrangement of
FIG. 3
is limited to only being able to test 3 die at a time. Testing 300 die on a wafer with this 3 die per test limitation would require having to relocate the probe mechanism
301
approximately 100 ti
Bassuk Lawrence J.
Brady W. James
Nguyen Jimmy
Pert Evan
Telecky , Jr. Frederick J.
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