Computer-aided design and analysis of circuits and semiconductor – Integrated circuit design processing – Physical design processing
Reexamination Certificate
2008-11-05
2011-11-01
Lin, Sun J (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Integrated circuit design processing
Physical design processing
C716S108000, C716S134000, C716S136000
Reexamination Certificate
active
08051399
ABSTRACT:
An aspect of the present invention selects a maximum voltage and a minimum voltage in respective sub-intervals of a timing window in which an output of a cell is expected to switch, and performing timing analysis based on the selected maximum voltage and the selected minimum voltage. By using appropriate smaller sub-intervals within the timing window, more optimal physical layout of the design may be obtained. In an embodiment, the sub-intervals equal a cell delay, i.e., a delay between an input change to an output change for a corresponding cell. According to another aspect of the present invention, the sub-interval for later cells in a timing path are modified based on a modified timing window of previous cells in the timing path, to reduce the computational requirement.
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Ramakrishnan Venkatraman
Udayakumar H
Veeravalli Arvind Nembili
Vishweshwara Ramamurthy
Brady W. James
Lin Sun J
Marshall, Jr. Robert D.
Telecky , Jr. Frederick J.
Texas Instruments Incorporated
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