IC chip with nanowires

Active solid-state devices (e.g. – transistors – solid-state diode – Thin active physical layer which is – Heterojunction

Reexamination Certificate

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Details

C257SE27051, C257SE27073, C257SE29020, C257SE29024, C257SE29070, C257SE29327, C257S910000, C257S922000

Reexamination Certificate

active

10902486

ABSTRACT:
Arrangement of nanowires with PN junctions between bit lines and word lines are arranged as a ROM memory cell array. A number of the nanowires have dielectric regions and are present only as a dummy. The connections between word and bit lines may also exist as transistors which turn on or turn off only when a gate voltage is applied. A number of these transistors are constructed in complementary fashion and/or have insulating regions built in and serve as a dummy.

REFERENCES:
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patent: 6614080 (2003-09-01), Vajana et al.
patent: 6806141 (2004-10-01), Kamins
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patent: 2003/0122133 (2003-07-01), Choi et al.
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patent: WO-01/57917 (2001-08-01), None
patent: WO-03/063208 (2003-07-01), None
Cui, Yi., et al.: “High Performance Silicon Nanowire Field Effect Transistors”; Nano Letters, received Nov. 1, 2002; DOI: 10.1021
l0258751.
Cui, Yi., et al.: “Diameter-controlled synthesis of single-crystal silicon nanowires”; Applied Physics Letters, vol. 78, No. 15, Apr. 9, 2001, pp. 2214-2216.

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