IC chip

Details IC chip IC chip

2001-12-14

2003-01-21

Ngô, Ngân V. (Department: 2814)

Active solid-state devices (e.g., transistors, solid-state diode

With means to control surface effects

Insulating coating

C257S690000, C257S698000

Reexamination Certificate

active

06509628

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to an IC chip in which the position of a power source terminal can be changed.
BACKGROUND OF THE INVENTION
One of the measures against a common mode noise on an application substrate is to insert a bypass capacitor between power source terminals in an IC chip. Insertion of a bypass capacitor can reduce an unnecessary radiation noise adversely affecting an FM radio bandwidth, on which importance is placed from the viewpoint of an application. However, a stray inductance component caused by pattern wiring on a printed circuit board is actually inserted in series in the bypass capacitor, thereby canceling a noise reducing effect of the bypass capacitor. Therefore, it is necessary to dispose the bypass capacitor immediately near an IC chip as possible so as to reduce the inductance component for the purpose of achievement of a sufficient noise reducing effect.
Normally, a terminal of a power source potential VDD and a terminal of a ground potential GND in an IC chip are arranged adjacent to each other. A distance between the adjacent terminals is, for example, about 0.5 mm. In contrast, the size of a bypass capacitor is generally 0.5 mm or greater. Consequently, as shown in
FIG. 1
, part of each of power source wirings
11
and
12
on a printed circuit board
1
has been conventionally bent such that an interval between the power source wiring
11
, to which the power source potential VDD is applied, and the power source wiring
12
, to which the ground potential GND is applied, is made to be equal to the size of a bypass capacitor
2
, and thus, the bypass capacitor
2
is disposed astride the power source wirings
11
and
12
. In
FIG. 1
, reference numeral
13
designates a signal wiring; reference numeral
3
designates an IC chip; reference numeral
31
designates a power source terminal, to which the power source potential VDD is applied; reference numeral
32
designates a power source terminal, to which the ground potential GND is applied; and reference numeral
33
designates a signal terminal.
In this case, the bypass capacitor
2
is disposed at a position apart from the IC chip
3
by the amount of bending of part of each of the power source wirings
11
and
12
, and therefore, the wiring length from the IC chip
3
to the bypass capacitor
2
cannot become shortest. Consequently, since a stray inductance component inserted in series in the bypass capacitor
2
cannot be sufficiently reduced, a noise reducing effect owing to the insertion of the bypass capacitor
2
is cancelled.
In view of this, it is desirable to dispose the bypass capacitor
2
immediately near the IC chip
3
as possible without bending part of each of the power source wirings
11
and
12
on the printed circuit board
1
. It may be considered to use a bypass capacitor
2
having a size corresponding to the interval between the power source wirings
11
and
12
. However, in this case, the size of the bypass capacitor
2
must be as small as about 0.5 mm. It is difficult to mount the bypass capacitor having such a size on the printed circuit board
1
within current parts mounting capability.
Thus, as shown in
FIG. 2
, in order to mount a bypass capacitor
2
having a size mountable on a printed circuit board
1
without bending part of each of power source wirings
11
and
12
on the printed circuit board
1
, the disposing position of a lead terminal in an IC chip
3
is varied in such a manner that an interval between power source terminals
31
and
32
in the IC chip
3
becomes equal to the size of the bypass capacitor
2
. In an example shown in
FIG. 2
, one signal terminal
33
is interposed between the power source terminals
31
and
32
, thereby widening the interval between the power source wirings
11
and
12
in such a manner as to become equal to the size of the bypass capacitor
2
.
In order to vary the disposing position of the power source terminal in the IC chip, as described above, a design need be changed such that the arrangement of a power source pad, to which a power source potential VDD is applied, and another power source pad, to which a ground potential GND is applied, on a semiconductor chip corresponds to the disposing position of the power source terminal in the IC chip.
However, the bypass capacitor is formed into a plurality of sizes, and therefore, it is necessary to prepare a plurality of kinds of IC chips on which the power source terminals are arranged in different manners, and further, a plurality of different patterns must be designed, thereby posing a problem that a development period of the IC chip becomes longer or a development cost becomes higher. In the present specification, the semiconductor chip signifies a chip cut off from a wafer, and the IC chip signifies the semiconductor chip enveloped in a package.
SUMMARY OF THE INVENTION
It is an object of the present invention to provide an IC chip in which power source terminals can be arranged in different manners with semiconductor chips fabricated based on one and the same design.
According to one aspect of the present invention, in a semiconductor chip, a second power source pad, to which a second power source potential is applied, is arranged adjacent to a first power source pad, to which a first power source potential is applied, and further, there is provided a third power source pad, to which the second power source potential is applied. Moreover, between the second power source pad and the third power source pad are interposed signal pads by the number corresponding to a size of an external part such as a bypass capacitor inserted between a power source terminal, to which the first power source potential is applied, and a power source terminal, to which the second power source potential is applied. Thereafter, the second power source pad or the third power source pad is selected according to the size of the external part, and then, is connected to the power source terminal, to which the second power source potential is applied, in an IC chip.
According to the above-mentioned aspect of present invention, the second power source pad or the third power source pad is selected as a power source pad, to which the second power source potential is applied, in the semiconductor chip, and then, the selected power source pad is electrically connected to the power source terminal, to which the second power source potential is applied, in the IC chip via a bonding wire. Consequently, the interval between the power source terminal, to which the first power source potential is applied, and the power source terminal, to which the second power source potential is applied, can be varied by an integral multiple of an interval between lead terminals in the IC chip according to the selected power source pad, in which the power source terminals are proximate to each other in the IC chip.
Other objects and features of this invention will become apparent from the following description with reference to the accompanying drawings.


REFERENCES:
patent: 5982043 (1999-11-01), Iwata
patent: 6201308 (2001-03-01), Ikegami et al.
patent: 62-5649 (1987-01-01), None
patent: 62-90956 (1987-04-01), None

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