Patent
1996-08-27
1999-01-26
Butler, Dennis M.
395557, 395559, G06F 104, G06F 124
Patent
active
058646957
DESCRIPTION:
BRIEF SUMMARY
FIELD OF THE INVENTION
The present invention relates to an IC card control circuit for controlling an operating state of an IC card, and an IC card control system.
BACKGROUND INFORMATION
What are known as integrated circuit card (hereinafter referred to as "IC card") reader/writers exist as prior art IC card control circuits for reading out IC card information and writing information to the IC card. Such conventional IC card reader/writers are mainly incorporated into Automatic Teller Machine (ATM) and Point Of Sale (POS) terminals.
However, because such conventional IC card reader/writers are incorporated into ATM or POS terminals, utilizing IC cards has been limited to ATM and POS terminals. Also, because it is necessary to design the conventional IC card reader/writers and IC cards exclusively for the ATM and POS terminals, the initial investment is very large. The spread of IC cards has been prevented for the reasons mentioned above.
In order to solve these problems, compact IC card reader/writers that can be connected to personal computers have recently been used. That is, general purpose IC card readers have been used.
SUMMARY OF THE INVENTION
In order to solve the above mentioned problems, according to one example of the present invention, there are provided a clock control circuit for receiving a control signal and delaying the received control signal by a first delay time, and outputting the delayed control signal as a clock control signal; a delayed signal generating circuit for receiving the control signal and delaying said control signal by a second delay time which is longer than the first delay time, and outputting said delayed control signal as a delayed circuit, a power supply control signal for outputting a power supply control signal in response to one of either the control signal or the delayed signal; and a reset control circuit for outputting a reset control signal in response to both the control signal and the delayed signal.
According to this example of the present invention, various signals for controlling the operating state of an IC card are generated from one control signal from a host, such as a personal computer, and two signals having a first and second time delay from this control signal.
That is, the various signals mentioned above are hardware generated based on the control signal.
BRIEF DESCRIPTION OF THE DRAWINGS
FIG. 1 is a block diagram of a first embodiment of the present invention.
FIG. 2 is a diagram showing the connection relationship of the IC card control circuit of the present invention.
FIG. 3 is a timing diagram showing the IC card activation/deactivation sequence.
FIG. 4 is a circuit diagram of the first embodiment of the present invention.
FIG. 5 is a timing chart for describing the operation of the circuit of FIG. 4.
FIG. 6 is a circuit diagram showing modified example 1 of the first embodiment of the present invention.
FIG. 7 is a timing chart for describing the operation of the circuit shown in FIG. 6.
FIG. 8 is a circuit diagram showing modified example 2 of the first embodiment of the present invention.
FIG. 9 is a circuit diagram showing modified example 3 of the first embodiment of the present invention.
FIG. 10 is a timing chart for describing the operation of the circuit shown in FIG. 9.
FIG. 11 is a circuit diagram showing modified example 4 of the first embodiment of the present invention.
FIG. 12 is a timing chart for describing the operation of the circuit shown in FIG. 4.
FIG. 13 is a block diagram of a second embodiment of the present invention.
FIG. 14 is a circuit diagram of the second embodiment of the present invention.
FIG. 15 is a timing chart for describing the operation of the circuit of FIG. 14.
FIG. 16 is a block diagram of a third embodiment of the present invention.
FIG. 17 is a circuit diagram of the third embodiment of the present invention.
FIG. 18 is a timing chart for describing the operation of the circuit of FIG. 17.
FIG. 19 is a circuit diagram showing modified example 1 of the third embodiment of the present inven
REFERENCES:
patent: 4464584 (1984-08-01), Hentzschel et al.
patent: 4528629 (1985-07-01), Breitling
patent: 5454114 (1995-09-01), Yach et al.
patent: 5513358 (1996-04-01), Lundberg et al.
Butler Dennis M.
OKI Electric Industry Co., Ltd.
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