I.sup.2 L interface with external inputs and method thereof

Details I.sup.2 L interface with external inputs and method thereof I.sup.2 L interface with external inputs and method thereof

1977-08-22

1979-06-19

Anagnos, Larry N.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307203, 307299B, 307DIG1, 357 92, H03K 1908, H03K 1920

Patent

active

041587820

ABSTRACT:
Combining a differential PNP transistor pair for receiving external digital signals with an NPN output transistor in an I.sup.2 L configuration connected to the output of the differential pair provides a simple, high-speed, and versatile digital logic to I.sup.2 L interface circuit. The interface circuit is applicable to almost any digital logic series and also to analog inputs as they provide inputs into I.sup.2 L circuitry.

REFERENCES:
patent: 3735151 (1973-05-01), Frederiksen
patent: 3755693 (1973-08-01), Lee
patent: 4005315 (1977-01-01), Blauschild
Hart et al., "Bipolar LSI Takes a New Direction with I.sup.2 L;" Electronics, (pub.); pp. 111-118; 10/3/74.
Robbins, "MTL-T.sup.2 L Parallel Clock Powering;" IBM Tech. Discl. Bull.; vol. 19, No. 6, pp. 2075-2076; 11/1976.
Muller et al., "High-Speed I.sup.2 L with Oxide Isolation;" Siemens Forsch. u. Entwickl.-Ber. Bd. 5, (1976), Nr. 6; pp. 360-363.
Hart et al., "Integrated Injection Logic: A New Approach to LSI;" IEEE-JSSC, vol. Sc-7, No. 5, pp. 346-351; 10/1972.

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