I.sup.2 L Integrated circuit and process of fabrication

Details I.sup.2 L Integrated circuit and process of fabrication I.sup.2 L Integrated circuit and process of fabrication

1978-02-07

1980-07-01

Wojciechowicz, Edward J.

357 49, 357 55, 357 92, H01L 2702

Patent

active

042109256

ABSTRACT:
In a complementary pair of bipolar transistors, one vertical and one lateral, the vertical transistor includes a heavily doped buried emitter, lightly doped buried graded base and a heavily doped surface collector and the lateral transistor includes a lightly doped substrate base and heavily doped emitter and collector. The lateral transistor's collector isolates the lateral transistor's base from the vertical transistor's collector.
This integrated circuit approach includes the I.sup.2 L structure of the present invention and T.sup.2 L devices. The I.sup.2 L transistors are in dielectrically isolated regions with the vertical transistors emitter being connected to the polycrystalline support through a vertical opening in the dielectric isolation.
The process of fabrication includes forming the vertical transistor's base by diffusion into a first surface of a substrate of opposite conductivity type, forming the vertical transistor's emitter epitaxially on the first surface and forming the vertical transistor's collector and the lateral transistor's emitter and collector by diffusion into the opposite surface of the substrate. The lateral transistor's collector diffusion is from the opposite surface down to the vertical transistor's base and separates the vertical transistor 's collector from the portion of the substrate which is the lateral transistor's base.
For integrated circuits, the process includes dividing the substrate into a plurality of dielectrically insulated regions after forming the epitaxial emitter and depositing a polycrystalline support.

REFERENCES:
patent: 3993513 (1976-11-01), O'Brien
patent: 4082571 (1978-04-01), Graul et al.
patent: 4140559 (1979-02-01), Van Vonno

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