I.sub.DDQ -testing of bias generator circuit

Details I.sub.DDQ -testing of bias generator circuit I.sub.DDQ -testing of bias generator circuit

1995-09-21

1998-05-12

Hecker, Stuart N.

Electricity: power supply or regulation systems

Self-regulating

Using a three or more terminal semiconductive device as the...

324537, 371 225, G05F 304, H01H 3102

Patent

active

057511411

ABSTRACT:
A bias generator is tested in an I.sub.DDQ -scheme by applying each respective one of the bias voltages to a respective PFET that is individually gated by a respective NFET. This permits measuring the quiescent currents. Any deviation in the bias voltages is translated into a deviation of the quiescent current.

REFERENCES:
patent: 5057774 (1991-10-01), Verhelst et al.
patent: 5371457 (1994-12-01), Lipp
patent: 5394026 (1995-02-01), Yu et al.
patent: 5459737 (1995-10-01), Andrews
patent: 5485095 (1996-01-01), Bertsch et al.
patent: 5497073 (1996-03-01), Bohme et al.

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