I/O structure for microprocessor implemented systems

Details I/O structure for microprocessor implemented systems I/O structure for microprocessor implemented systems

1974-09-09

1976-08-31

Shaw, Gareth D.

Communications: electrical

Digital comparator systems

G06F 304, G06F 910, G06F 912

Patent

active

039784550

ABSTRACT:
Apparatus for selecting the operational mode of a particular input/output device in an expandable modular electronic data processing system employing microprocessor devices and testing the I/O device without the use of additional input/output addresses. Input/output interface modules associated with corresponding ones of the I/O devices include a plurality of flip-flops having corresponding memory addresses associated therewith for testing and selecting the operational mode of the I/O device in accordance with the contents of the flip-flops.

REFERENCES:
patent: 3550133 (1970-12-01), King et al.
patent: 3593289 (1971-07-01), Lerch
patent: 3651484 (1972-03-01), Smeallie
patent: 3673576 (1972-06-01), Donaldson, Jr.
patent: 3714635 (1973-01-01), Hamilton et al.
patent: 3737869 (1973-06-01), Trelut et al.
patent: 3753243 (1973-08-01), Ricketts, Jr. et al.

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