I/O rack addressing error detection for process control

Details I/O rack addressing error detection for process control I/O rack addressing error detection for process control

1984-02-21

1986-06-17

Atkinson, Charles E.

Excavating

G06F 1110

Patent

active

045960143

ABSTRACT:
In an industrial process control system, in which the process is controlled via multiplicity of I/O data points communicating with a computer system controller, errors in the addressing signals selecting the I/O data points are prevented from causing the incorrect setting or reading out incorrect data from wrongly selected data points. A multibit parity signal is generated from the address signals as presented at the output of the computer controller and this parity signal is compared with a second multibit parity signal generated from the address signals as applied to the I/O racks on which the I/O data points are organized. If the parity signals don't compare, the change of the setting of or the read out of valid data from the I/O data point selected by the address signal is prevented. A strobe error detection system is provided in which a strobe pulse applied from the computer system controller to the I/O racks is routed back to the computer system controller where it is compared with the strobe pulse at the output of the computer system controller. The voltage level of the routed back signal is sensed at the leading edge of the strobe pulse at the output of the computer system controller and at the trailing edge of this strobe pulse. If the voltage levels of the routed back signal are not correct, an alarm signal is generated to indicate strobe error.

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