I/O port and RAM memory addressing technique

Details I/O port and RAM memory addressing technique I/O port and RAM memory addressing technique

1996-08-22

1999-07-20

Beausoliel, Jr., Robert W.

395856, G06F 1300

Patent

active

059266481

ABSTRACT:
A method and apparatus for addressing and writing data to extended I/O ports and additional RAM memory is provided, wherein a microprocessor sends both address and data information by way of a bus. The technique comprises the steps of writing to a first field of the bus an I/O port or RAM memory access code, to a second field of the bus an address for addressing a selected I/O port or RAM memory space for writing data thereto, and to a third field of the bus data which is to be written to the selected I/O port or RAM memory space; detecting whether the first field of the bus contains such access codes; decoding the address in the second field of the bus for selecting the selected I/O port; and writing data in third field of the bus to the selected I/O port or RAM memory if the access code has been detected.

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