I/O pad overvoltage protection circuitry

Details I/O pad overvoltage protection circuitry I/O pad overvoltage protection circuitry

2002-09-10

2004-03-02

Nguyen, Long (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Gating

Parallel controlled paths

C327S391000, C327S328000, C327S537000, C326S113000, C361S056000

Reexamination Certificate

active

06700431

ABSTRACT:

BACKGROUND OF THE INVENTION
The present invention relates generally to I/O circuits, and in particular to transmission gates with over-voltage protection.
The transmission gate is an integrated circuit which connects between an internal, core circuit and an I/O pad. The transmission gate circuit acts as a low-impedance connection to the pad under normal conditions where the supply voltage V
dd
is greater than the voltage at the pad, which is also greater than zero or ground. However, when the I/O pad is subject to voltage spikes, or acts as an input, it is possible that its voltage may exceed that of the supply voltage. For example, a chip designed with a 3.3 volt power supply may be connected to another chip which uses 5-volt levels.
FIG. 1
illustrates a prior art transmission gate circuit. NMOS transmission gate transistor M
10
and PMOS transmission gate transistor M
9
connect core circuitry
10
to an I/O pad
12
. The P-well
14
of transistor M
10
is connected to ground, while the N-well
16
of transistor M
9
is connected to the power supply, V
dd
.
During normal conditions, when V
dd
is greater than the voltage at the pad, V
pad
, which is greater than zero, the transmission gate is on. If the voltage at the pad should exceed the supply voltage by more than a threshold amount, the P-channel transistor M
10
is still on, effectively connecting pad terminal
12
to the internal core circuit. Thus, this circuit does not isolate the internal circuitry from the I/O pad when the pad voltage exceeds the supply voltage. If the voltage on the pad is greater than the supply voltage, the intrinsic PN diode between the source and the bulk (P-well
16
) of transistor M
9
will turn on, shorting pad
12
to V
dd
. Alternately, the channel of PMOS transistor M
9
can simply turn on due to negative gate-to-source potential with the gate at zero and the source at a positive potential.
BRIEF SUMMARY OF THE INVENTION
The present invention provides a protection circuit for a transmission gate having a PMOS transmission gate transistor and an NMOS transmission gate transistor coupled between a core circuit and an I/O pad. A biasing transistor is coupled to a gate of the NMOS transmission gate transistor to turn it on during normal operation. A protection circuit will turn off the NMOS transmission gate transistor when the voltage at the pad exceeds the supply voltage by more than a threshold amount. This protection circuit includes a first protection transistor coupled between the gate of the biasing transistor and the pad to turn the biasing transistor off when the voltage on the pad exceeds the supply voltage by more than the threshold amount.
In one embodiment, one or more NMOS protection transistors are coupled between the gate of the PMOS transmission gate transistor and ground, with the gate of the PMOS transmission gate transistor being connected to the first protection transistor. In addition, an N-well biasing circuit is provided with a PMOS transistor coupled between the N-well and the pad, with the gate coupled to the supply voltage. Additionally, a second PMOS transistor is connected between the supply voltage V
dd
and the N-well, with its gate connected to the first protection transistor.
In one embodiment, a second NMOS transmission gate transistor is added to limit the voltage drop across the first NMOS transmission gate transistor.
For a further understanding of the nature and advantages of the invention, reference should be made to the following description taken in conjunction with the accompanying drawings.


REFERENCES:
patent: 5563540 (1996-10-01), Ashley et al.
patent: 5617055 (1997-04-01), Confalonieri et al.
patent: 5914627 (1999-06-01), Fotouhi
patent: 5926056 (1999-07-01), Morris et al.
patent: 6037828 (2000-03-01), Fotouhi
patent: 6137311 (2000-10-01), Hedberg

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