Computer graphics processing and selective visual display system – Computer graphic processing system – Integrated circuit
Reexamination Certificate
2001-12-27
2004-09-14
Tung, Kee M. (Department: 2676)
Computer graphics processing and selective visual display system
Computer graphic processing system
Integrated circuit
C345S520000
Reexamination Certificate
active
06791554
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to computer system graphics and, more particularly, to I/O nodes including integrated graphics functionality.
2. Description of the Related Art
In a typical computer system, one or more processors may communicate with input/output (I/O) devices over one or more buses. The I/O devices may be coupled to the processors through an I/O bridge which manages the transfer of information between a peripheral bus connected to the I/O devices and a shared bus connected to the processors. Additionally, the I/O bridge may manage the transfer of information between a system memory and the I/O devices or the system memory and the processors.
Unfortunately, many bus systems suffer from several drawbacks. For example, multiple devices attached to a bus may present a relatively large electrical capacitance to devices driving signals on the bus. In addition, the multiple attach points on a shared bus produce signal reflections at high signal frequencies which reduce signal integrity. As a result, signal frequencies on the bus are generally kept relatively low in order to maintain signal integrity at an acceptable level. The relatively low signal frequencies reduce signal bandwidth, limiting the performance of devices attached to the bus.
Lack of scalability to larger numbers of devices is another disadvantage of shared bus systems. The available bandwidth of a shared bus is substantially fixed (and may decrease if adding additional devices causes a reduction in signal frequencies upon the bus). Once the bandwidth requirements of the devices attached to the bus (either directly or indirectly) exceeds the available bandwidth of the bus, devices will frequently be stalled when attempting access to the bus, and overall performance of the computer system including the shared bus will most likely be reduced. An example of a shared bus used by I/O devices is a peripheral component interconnect (PCI) bus.
To overcome some of the drawbacks of a shared bus, some computers systems may use packet-based communications between devices or nodes. In such systems, nodes may communicate with each other by exchanging packets of information. In general, a “node” is a device which is capable of participating in transactions upon an interconnect. For example, the interconnect may be packet-based, and the node may be configured to receive and transmit packets. Generally speaking, a “packet” is a communication between two nodes: an initiating or “source” node which transmits the packet and a destination or “target” node which receives the packet. When a packet reaches the target node, the target node accepts the information conveyed by the packet and processes the information internally. A node located on a communication path between the source and target nodes may relay or forward the packet from the source node to the target node.
Additionally, there are systems that use a combination of packet-based communications and bus-based communications. For example, a computer system may connect to a graphics adapter through a graphics bus such as an accelerated graphics port (AGP) bus. The graphics bus may be connected to an AGP interface that may translate AGP transactions into packet transactions. The AGP interface may communicate with a host bridge associated with one of the processors for access to a system memory.
Many processors connect to the system graphics engine via an AGP port embedded in a system controller. The system controller may be manufactured on one integrated circuit chip that may be part of a chipset. In the case of a system using I/O nodes, the I/O node may be manufactured in an integrated circuit chip. The integrated circuit chip containing the I/O node may include an AGP interface for connection to a graphics bus and ultimately to a graphics adapter. In systems using I/O nodes connected to the system processor through a packet bus, an interface such as the AGP interface may have some latency associated with it, thus an I/O node that may use the packet bus for graphics transactions may be desirable.
SUMMARY OF THE INVENTION
Various embodiments of an I/O node for a computer system including an integrated graphics engine are disclosed. In one embodiment, an input/output node for a computer system that is implemented on an integrated circuit chip includes a first transceiver unit, a second transceiver unit, a packet tunnel, a graphics engine and a graphics interface.
The first transceiver unit may be configured to receive and transmit packet transactions on a first link of a packet bus. The second transceiver unit may be coupled to receive and transmit packet transactions on a second link of the packet bus. The packet tunnel is coupled to convey selected packet transactions between the first transceiver unit and the second transceiver unit. The graphics engine is coupled to receive graphics packet transactions from the first transceiver unit and may be configured to render digital image information in response to receiving the graphics transactions. The graphics engine may further provide display signals corresponding to the digital image information for display on a display device such as an RGB monitor or an LCD screen, for example. The graphics interface is coupled to receive additional graphics packet transactions from the first transceiver unit and may be configured to translate the additional graphics packet transactions into transactions suitable for transmission upon a graphics bus, such as an AGP bus.
In one particular implementation, the I/O node further includes a control unit that is coupled to control the conveyance of the selected packet transactions between the first transceiver unit and the second transceiver unit. Further the control unit may be coupled to control the conveyance of the graphics packet transactions and the additional graphics packet transactions between the first transceiver unit and the graphics engine and between the first transceiver unit and the graphics interface, respectively. In another implementation, the graphics engine includes a configuration register, which may provide a user selectable bit for enabling and disabling the graphics engine.
In another embodiment, the first transceiver unit may be configured to receive and transmit packet transactions on a first link of a packet bus. The second transceiver unit may be coupled to receive and transmit packet transactions on a second link of the packet bus. The packet tunnel is coupled to convey selected packet transactions between the first transceiver unit and the second transceiver unit. The graphics interface is coupled to receive graphics packet transactions from the first transceiver unit and may be configured to translate the packet transactions into transactions suitable for transmission upon a graphics bus, such as an AGP bus. The graphics engine is coupled to receive graphics transactions from the graphics interface and may be configured to render digital image information in response to receiving the graphics transactions. The graphics engine may further provide display signals corresponding to the digital image information for display on a display device such as an RGB monitor or an LCD screen, for example.
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U.S. patent application Ser. No. 09/978,349 Filed Oct. 15, 2001.
U.S. patent application Ser. No. 10/093,146 Filed Mar. 7, 2002.
Gulick Dale E.
Hewitt Larry D.
Mergard James
Advanced Micro Devices , Inc.
Curran Stephen J.
Kivlin B. Noäl
Meyertons Hood Kivlin Kowert & Goetzel, P
Tung Kee M.
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