I/O Interrupt sequencing for real time and burst mode devices

Details I/O Interrupt sequencing for real time and burst mode devices I/O Interrupt sequencing for real time and burst mode devices

1978-10-02

1981-06-23

Zache, Raulfe B.

Boots, shoes, and leggings

G06F 300

Patent

active

042754402

ABSTRACT:
An improved I/O interrupt sequencing method and apparatus including generation of an instruction priority request signal to indicate that a real time task requires programmed I/O service. Generating an end of chain signal to suspend burst I/O control of the I/O bus and allow programmed I/O service to a real time device, and resetting the instruction priority request signal to allow burst mode data transfer to continue at the count positions at which it was suspended.

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patent: 3866181 (1975-02-01), Gayman et al.
patent: 3961312 (1976-06-01), Bodner et al.
Bodner, R. E. et al., "Multiple Class Cycle Steal System", IBM T.D.B., vol. 17, No. 10, Mar. 1975, DS US 049.
Miller, T. H. et al., "Interleaved Cycle Steal Burst Circuitry", IBM T.D.B., vol. 17, No. 9, Feb. 1975, pp. 2732-2735.

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