I/O interrupt handling mechanism in a multiprocessor system

Details I/O interrupt handling mechanism in a multiprocessor system I/O interrupt handling mechanism in a multiprocessor system

1987-07-21

1989-05-23

Heckler, Thomas M.

Boots, shoes, and leggings

3642302, 3642413, G06F 1324

Patent

active

048335983

ABSTRACT:
In a multiprocessor system in which a plurality of instruction processors (IP's) share a main storage (MS) and a channel controller (CHC) through a system controller (SC), when an I/O interrupt request is issued, IP's connected to the SC are examined to determine whether each of the IP's is executing an instruction which permits acceptance of the I/O interrupt request during the execution of the instruction. If one of the IP's is not executing such an instruction and can accept the I/O interrupt request, that IP will be selected.

REFERENCES:
patent: 4271468 (1981-06-01), Christensen et al.
patent: 4644465 (1987-02-01), Imamura

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