Boots – shoes – and leggings
Patent
1992-05-08
1995-05-09
Shin, Christopher B.
Boots, shoes, and leggings
364DIG1, 3642416, 364239, G06F 1300
Patent
active
054148146
ABSTRACT:
A computer interface is provided to support communication between a VMEbus architecture and a computer having its input/output (I/O) interface based on MIL-STD 1397B Type D or E asynchronous serial data specifications. A dual port RAM provides temporary storage for VMEbus data being transferred to the computer and computer data being transferred to the VMEbus. Both the VMEbus data and computer data are stored in a VMEbus parallel format. An interrupt controller is responsive to interrupt control signals on the VMEbus and a local bus. The interrupt controller places a processor interrupt on the local bus in response to an interrupt control signal on the VMEbus, and places a VME interrupt on the VMEbus in response to an interrupt control signal on the local bus. A processor, responsive to the processor interrupt, generates a write control signal and transfers the VMEbus data stored in the dual port RAM onto the local bus. An interface controller, responsive to the write control signal and a select signal indicative of one of the type D or E I/O interface specifications, converts the VMEbus data transferred onto the local bus into asynchronous serial data in accordance with MIL-STD 1397B. The interface controller also is responsive to a request-to-send control signal from the computer to convert asynchronous serial data from the computer into computer data. The processor, also responsive to the request-to-send control signal, generates a read control signal and the interrupt control signal on the local bus. The interface controller, responsive to the read control signal, transfers the computer data to the dual port RAM via the local bus.
REFERENCES:
patent: 4569062 (1986-02-01), Dellande et al.
patent: 4604682 (1986-08-01), Schwan et al.
patent: 4625307 (1986-11-01), Tulpule et al.
patent: 4642761 (1987-02-01), Yanagiuchi et al.
patent: 4644462 (1987-02-01), Matsubara et al.
patent: 4695952 (1987-09-01), Howland
patent: 4700292 (1987-10-01), Campanini
patent: 4750149 (1988-06-01), Miller
patent: 4794520 (1988-12-01), Kobus, Jr. et al.
patent: 4794525 (1988-12-01), Pickert et al.
patent: 4873626 (1989-10-01), Gifford
patent: 4933835 (1990-06-01), Sachs et al.
patent: 4939735 (1990-07-01), Fredericks et al.
patent: 4977494 (1990-12-01), Gabaldon et al.
patent: 4999787 (1991-03-01), McNally et al.
patent: 5047921 (1991-09-01), Kinter et al.
patent: 5131272 (1992-07-01), Minei et al.
patent: 5134702 (1992-07-01), Charych et al.
patent: 5175819 (1992-12-01), Le Ngoc et al.
patent: 5226173 (1993-07-01), Sasaki et al.
patent: 5247652 (1993-09-01), Uda
patent: 5283869 (1994-02-01), Adams et al.
Military Standard 1397B(Navy), 3 Mar. 1989, Sections 5.3 and 5.4 particuly relevant.
Shin Christopher B.
Shuster Jacob
The United States of America as represented by the Secretary of
LandOfFree
I/O interface between VME bus and asynchronous serial data compu does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with I/O interface between VME bus and asynchronous serial data compu, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and I/O interface between VME bus and asynchronous serial data compu will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-1712412