I/O device interface having buffer mapped in processor memory ad

Details I/O device interface having buffer mapped in processor memory ad I/O device interface having buffer mapped in processor memory ad

1991-10-22

1995-08-22

Lee, Thomas C.

Boots, shoes, and leggings

364DIG1, 364239, 3642383, G06F 1300, G06F 1312

Patent

active

054448522

ABSTRACT:
An I/O device includes a memory and a transmission reception control circuit addresses on the memory space are assigned to the memory. The transmission reception control circuit includes a plurality of registers to which addresses on the I/O space are assigned. The memory stores data to be transmitted to an external equipment or data received from the external equipment. The plurality of registers hold control data. The memory and the transmission reception control circuit are selectively activated in response to an identification signal. The transmission reception control circuit reads out data to be transmitted to the external equipment from the memory or writes data received from the external equipment into the memory in response to the control data held in the plurality of registers.

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"PC-Hardwarebuch", by Hans-Peter Messmer, Addison-Wesley Publishing Co., Bonn 1992, pp. 134-136.
Intel Corporation, Hardware Reference Manual, 1987, p. 8-1.

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