I/O circuit of semiconductor integrated device

Details I/O circuit of semiconductor integrated device I/O circuit of semiconductor integrated device

2001-05-31

2002-09-17

Tran, M. (Department: 2818)

Static information storage and retrieval

Format or disposition of elements

C365S063000

Reexamination Certificate

active

06452827

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to an I/O circuit of a semiconductor integrated circuit device whose I/O circuit is employed as an input circuit for inputting to an internal circuit of the semiconductor integrated circuit device, a signal input from an external circuit thereof, or as an output circuit forouteputting to the external circuit, a signal output from the internal circuit, and more particularly relates to the I/O circuit that operates effectively when a signal voltage higher than the voltage of an internal power supply of the semiconductor integrated circuit device is input from the external circuit.
2. Description of the Related Art
FIG. 4
shows a circuit diagram of a conventional input circuit. The input circuit of
FIG. 4
is provided inside a semiconductor integrated circuit device (an LSI chip), and inputs a signal input from an external circuit to a pad electrode PAD, from a node OUT to an internal circuit of the LSI chip. An internal power supply VDD is 3[V]. The external circuit inputs a low level (“L” level) signal of 0[V] or a high level (“H” level) signal of 5[V] to a pad electrode PAD, or sets the pad electrode PAD at a high impedance (“Z” level). Here, the high impedance (“Z” level) means that the pad electrode PAD (node I/O) is floating with respect to the external circuit, and with respect to all of the circuits connected to the node (I/O).
In the input circuit in
FIG. 4
, PMOS transistor P
11
and NMOS transistor N
15
are OFF all the time. These transistors are provided such that the input circuit of
FIG. 4
can be converted to be used as an output circuit easily. When the input circuit of
FIG. 4
is used as an output circuit, the transistors are ON/OFF in accordance with a signal input from the internal circuit to respective gate electrodes.
Substrates of PMOS transistors P
12
to P
17
(N-well layers on which the PMOS transistors P
12
to P
17
are formed) are connected to a node W
11
which is floating with respect to the internal power supply VDD. Accordingly, even when a signal voltage of 5[V], higher than the internal power supply VDD, is input to the pad electrode PAD, flowing of leakage current from the pad electrode PAD to the internal power supply VDD through a pn junction is prevented. The pn junction is formed by source or drain, and a substrate, N-well layer, of PMOS. Further, the PMOS transistors P
12
and P
15
are OFF when a signal voltage of 5[V] higher than the internal power supply VDD is input to the pad electrode PAD, thereby preventing electric current from flowing in reverse from the pad electrode PAD to the internal power supply VDD.
The PMOS transistors P
13
, P
14
, NMOS transistors N
11
to N
13
, and an inverter INV
11
convert a signal of 5[V], which was input from the external circuit to the pad electrode PAD, to a signal of substantially 3[V] on the basis of a VIH standard of an internal circuit, and inputs the converted signal to the internal circuit. The VIH standard is one determining voltage tolerance of an “H” level input signal.
The NMOS transistors N
11
and N
14
are provided so as to prevent a voltage greater than or equal to the internal power supply VDD from being applied through drain-source, gate-drain, and gate-source, of each of the NMOS transistors N
12
and N
15
when a signal of 5[V] is input to the pad electrode PAD. Accordingly, the NMOS transistors N
11
and N
14
can deal even with an LSI chip manufactured through a process in which voltage tolerance is low.
The PMOS transistor P
16
is ON when a signal of 5[V] is input to the pad electrode PAD, and sets the node W
11
, each substrate of the PMOS transistors P
12
to P
17
, at 5[V].
NMOS transistor N
16
and PMOS transistor P
17
clamp the node I/O at substantially 3[V] when the pad electrode PAD is at the “Z” level. Further, since the PMOS transistor P
17
is ON when the pad electrode PAD is 0[V] (the “L” level) or 5[V] (the “H” level), electric current flows between the internal power supply VDD and the pad electrode PAD through a source-drain of the PMOS transistor P
17
.
However, in the above-described conventional circuit, when the pad electrode PAD is at the “L” level, a node S
14
is at the “L” level, and the PMOS transistors P
12
and P
15
are ON, an electric current route I
1
(see
FIG. 4
) of [VDD]-[source of P
17
]-[substrate of P
17
]-[W
11
]-[drain of P
15
]-[S
13
]-[P
12
]-[PAD] is formed. Accordingly, there has been a problem in that electric current flowing into the pad electrode PAD becomes larger than a predetermined value (the value of current flowing through the source-drain of the PMOS transistor P
17
), and consumption of electric current thereby increases. Moreover, the PMOS transistor P
15
is provided so as to set the node W
11
at the same potential as the internal power supply VDD when the circuit of
FIG. 4
is used as an output circuit and the PMOS transistor P
11
is ON.
When the pad electrode PAD changes from the “L” level to the “Z” level, the potential of the node I/O is increased by the PMOS transistor P
17
. However, there have been problems, described below. Namely, as the potential of the node I/O nears the potential of the internal power supply VDD, the potential of the node Sll also increases, electric current characteristics of the PMOS transistor P
17
thereby deteriorate, and it takes more time until the node I/O reaches the potential of the internal power supply VDD as compared to a case in which a pull-up transistor (in which the gate electrode of the PMOS transistor P
17
is fixed at the “L” level) having the same dimensions as the PMOS transistor P
17
is employed. Further, because increasing dimensions of the PMOS transistor P
17
means increasing electric current consumption, it is not preferable.
Since PMOS and NMOS usually have different thresholds, there have been problems in that, according to a combination of thresholds of the PMOS transistor P
17
and the NMOS transistor N
16
, the PMOS transistor P
17
may be OFF before the node I/O increases to the potential of the internal power supply VDD (3[V]) so that the node I/O does not reach to the power supply potential. If the node I/O does not reach the power supply potential (3[V]), a drawback is generated in that a margin for the VIH standard of a signal input from a node OUT to the internal circuit is reduced, or the like.
In order to solve such a conventional problem as described above, the present invention is achieved, and it is an object of the present invention to reduce electric current consumption. Further, it is another object of the present invention to set this node at the potential of the internal power supply reliably when a connecting node of an external circuit is at high impedance.
SUMMARY OF THE INVENTION
In order to accomplish the above-described objects, in accordance with an aspect of the present invention, there is provided an I/O circuit of a semiconductor integrated circuit device, comprising: a first MOS transistor (P
11
) whose gate electrode is connected to a first node (IN
1
) to which a first signal is input from at least one of a first power supply (VDD) and an internal circuit, of the semiconductor integrated circuit device, whose first electrode and substrate are connected to said first power supply, and whose second electrode is connected to a second node (S
13
); a second MOS transistor (P
12
) whose first electrode is connected to said second node, whose gate electrode is connected to a third node (S
14
), whose second electrode is connected to a fourth node (I/O) to which a signal is either input from an external circuit or from which a signal is output to the external circuit, and whose substrate is connected to a fifth node (W
11
) which is floating with respect to said first power supply; a third MOS transistor (P
15
) whose f

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