I/O cell for programmable logic device providing latched, unlatc

Details I/O cell for programmable logic device providing latched, unlatc I/O cell for programmable logic device providing latched, unlatc

1993-02-23

1994-05-31

Hudspeth, David R.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307243, 307443, H03K 19177

Patent

active

053172108

ABSTRACT:
An input/output cell for interconnecting an I/O pad with internal circuitry in a programmable logic device provides clocked and unclocked inputs through an internal bus to selected logic array blocks. The input/output cell further includes a fast input line in which the I/O pad is directly connected with a selected logic array block without travelling through the latch circuitry of the I/O cell and the internal bus of the programmable logic device.

REFERENCES:
patent: 4987319 (1991-01-01), Kawana
patent: 4992676 (1991-02-01), Takata et al.
patent: 5017813 (1991-05-01), Galbraith et al.
patent: 5023484 (1991-06-01), Pathak et al.
patent: 5245226 (1993-09-01), Hood, Jr. et al.

Affiliated with

Also associated with

Rating

I/O cell for programmable logic device providing latched, unlatc does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with I/O cell for programmable logic device providing latched, unlatc, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and I/O cell for programmable logic device providing latched, unlatc will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-1629782