I/O cell and ESD protection circuit

Details I/O cell and ESD protection circuit I/O cell and ESD protection circuit

2005-01-04

2005-01-04

Nelms, David (Department: 2818)

Active solid-state devices (e.g., transistors, solid-state diode

Regenerative type switching device

Device protection

C257S175000, C257S355000

Reexamination Certificate

active

06838708

ABSTRACT:
An ESD protection circuit has a VDD bus, a VSS bus, an IC pad, a PMOS transistor coupled to the IC pad and the VDD bus, and an NMOS transistor coupled to the IC pad and the VSS bus. The pitch of the PMOS can smaller than the pitch of the NMOS, and the drain-contact-to-gate-spacing (DCGS) for the PMOS can be smaller than the DCGS for the NMOS.

REFERENCES:
patent: 5248892 (1993-09-01), Van Roozendaal et al.
patent: 5721439 (1998-02-01), Lin
patent: 6046087 (2000-04-01), Lin et al.
patent: 6064095 (2000-05-01), Fu
patent: 6153913 (2000-11-01), Hsu et al.
patent: 6157065 (2000-12-01), Huang et al.
patent: 6236073 (2001-05-01), Hsu
patent: 20040080339 (2004-04-01), Kubo

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