I/O bus expansion system wherein processor checks plurality of p

Details I/O bus expansion system wherein processor checks plurality of p I/O bus expansion system wherein processor checks plurality of p

1996-02-01

1999-01-12

Lee, Thomas C.

395822, 395830, 395837, 395866, G06F 1314, G06F 1322

Patent

active

058600280

ABSTRACT:
A processing system including a processor and a peripheral wherein a configuration input of an address decoder or a device address input of a peripheral device which is not needed to set the peripheral's device address is used to increase the input capability of the processor. A data input signal is coupled to the configuration input or to the device address input such that the peripheral has a plurality of possible device addresses dependent on the state of the data input signal. The processor is configured to attempt communication with the peripheral by checking the plurality of possible device addresses of the peripheral until the peripheral gives a response to the processor. The device address to which the peripheral responds represents the state of the data input signal.

REFERENCES:
patent: 4315308 (1982-02-01), Jackson
patent: 4628480 (1986-12-01), Floyd
patent: 5359717 (1994-10-01), Bowles et al.

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