I/O buffer circuit

Details I/O buffer circuit I/O buffer circuit

2005-03-29

2005-03-29

Wells, Kenneth B. (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Current driver

C327S333000, C326S062000, C326S081000

Reexamination Certificate

active

06873189

ABSTRACT:
In an I/O buffer circuit for solving problems occurred due to I/O voltage level difference, the I/O buffer circuit includes a logical controller for generating an enable signal and data according to an internal core voltage (VDDC); a level converter for converting the internal core voltage (VDDC) into an output voltage level when the internal core voltage (VDDC), an input signal voltage (VDDI) and an output signal voltage (VDDO) are different; and a pull-up unit for permitting a voltage level in specific level order through the level converter when a power voltage level in a semiconductor chip and a voltage level of an input signal are different from each other.

REFERENCES:
patent: 5467031 (1995-11-01), Nguyen et al.
patent: 5781026 (1998-07-01), Chow
patent: 6262599 (2001-07-01), Coughlin, Jr. et al.
patent: 6611155 (2003-08-01), Sterrantino
Hyun Lee, “CMOS I/O Transceiver With 3V/5V Level Converter and N-Tub Voltage Generator”, ASIC Conference and Exhibit, 1993, Proceedings, 6thAnnual IEEE International, pp. 444-447 (Sep., 1993).

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