I/O architecture for integrated circuit package

Details I/O architecture for integrated circuit package I/O architecture for integrated circuit package

2005-05-24

2005-05-24

Parekh, Nitin (Department: 2811)

Active solid-state devices (e.g., transistors, solid-state diode

Housing or package

With contact or lead

C257S690000, C257S691000, C257S692000, C257S695000, C257S697000, C257S698000, C257S778000

Reexamination Certificate

active

06897556

ABSTRACT:
A circuit package may include an upper surface of first conductive elements and second conductive elements. The first conductive elements may receive input/output signals from respective conductive elements of an integrated circuit die, and the second conductive elements may receive a first plurality of the input/output signals from respective ones of the first conductive elements. A lower surface of the package may include third conductive elements, the third conductive elements to receive a second plurality of the input/output signals from respective other ones of the first conductive elements.

REFERENCES:
patent: 3612744 (1971-10-01), Thomas
patent: 3757029 (1973-09-01), Marshall
patent: 6776658 (2004-08-01), Tang
Mahajan, Ravi et al., “The Evolution of Microprocessor Packaging”, Intel Technology Journal Q3, 2000. 10pgs.
Lii, Mirng-Ji et al., “Flip-Chip Technology on Organic Pin Grid Array Packages”, Intel Technology Journal Q3, 2000. 9pgs.
Polka, Lesley et al., “Package-Level Interconnect Design for Optimum Electrical Performance”, Intel Technology Journal Q3, 2000. 17pgs.

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