I-C Wafer incorporating junction-type field-effect transistor

Details I-C Wafer incorporating junction-type field-effect transistor I-C Wafer incorporating junction-type field-effect transistor

1979-12-14

1981-05-05

Edlow, Martin H.

357 41, 357 48, 357 59, H01L 2980

Patent

active

042662338

ABSTRACT:
A silicon wafer incorporating several semiconductor components, among them a junction-type field-effect transistor (J-FET) of low pinch-off voltage connectable as a resistor, comprises a substrate of P-type conductivity with an insular layer of N.sup.+ conductivity penetrated by one or more enclaves of substrate material. Thereafter, a stratum of N-doped silicon is epitaxially grown on the substrate, with formation of rising zones above each enclave and around the buried N.sup.+ layer which are heavily doped with P-type impurities to act as source connections or sinkers for an FET channel formed by the enclave or enclaves and as a barrier junction surrounding a section of the N-doped stratum which becomes the gate of the FET while the substrate serves as the drain.

REFERENCES:
patent: 4095252 (1978-06-01), Ochi
patent: 4115793 (1978-09-01), Nishizawa
patent: 4170019 (1979-10-01), Hysell
patent: 4181542 (1980-01-01), Yoshida

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