Semiconductor device manufacturing: process – Making passive device – Resistor
Reexamination Certificate
1999-10-28
2002-04-02
Niebling, John F. (Department: 2812)
Semiconductor device manufacturing: process
Making passive device
Resistor
C438S381000, C438S382000, C438S385000
Reexamination Certificate
active
06365482
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to the field of integrated circuit (I.C.) fabrication methods, and particularly to fabrication processes that include the formation of thin film resistors.
2. Description of the Related Art
“Thin film” processing is used to create structures or features on an integrated circuit wafer from a thin layer of material that has been deposited on top of an oxide layer formed on a substrate. Resistors, for example, are commonly fabricated using thin film techniques.
Present thin film processing methods, discussed, for example, in A. Grebene,
Bipolar and MOS Analog Circuit Design,
John Wiley & Sons (1984) pp. 22-26, possess several inherent characteristics that can adversely affect the performance of the resistors they are used to create. Thin film resistors, particularly those made from silicon chromium carbide (SiCrC), are fabricated per the following “back-end” process steps, i.e., steps performed after an I.C.'s active devices have been formed:
1. Contact Mask. With an oxide layer formed atop a silicon substrate, a contact mask step opens holes in the oxide where metal is to make contact to the silicon, for connection to the diffused terminals of a transistor, for example.
2. Sputter Platinum/sinter/strip. This step forms platinum silicide (PtSi
2
) wells at the bottom of the contact openings made in step 1. First, platinum is sputtered on the wafers. Next, a sinter is performed in which the platinum is annealed at about 500° C. for about 30 minutes in dry nitrogen (N
2
). During anneal, the platinum reacts with the silicon substrate and forms the PtSi
2
wells. After anneal, unreacted platinum is stripped, typically with a solution containing hydrochloric acid (HCl) and nitric acid (HNO
3
).
3. Sputter Thin Film (TF). Here, the actual resistor material, typically SiCrC, is sputtered on the wafer.
4. Sputter Titanium Tungsten (TiW) and Aluminum Copper (AlCu). TiW is sputtered first, to provide a thin (~900 Å) barrier layer under the metal which helps with electromigration and current density, as well as improving the contacts to the TF resistor material. AlCu is then sputtered (at about 400° C.) on top of the TiW; it is the primary metal and carries the resistor current.
5. Metal
1
(M
1
) Mask. This step dry etches AlCu, TiW and SiCrC according to the M
1
mask pattern to define the chip's metal traces and the boundaries of the TF resistors.
6. Thin Film Open Mask (TFOP). AlCu and TiW over the resistors are wet etched with hot phosphoric acid and hydrogen peroxide, respectively. This step removes material all the way down to the resistors' surface.
7. Plasma Enhanced Chemical Vapor Deposition (PECVD) Oxide Deposition I. A phosphorous-doped PECVD oxide is used between the M
1
and Metal
2
(M
2
) layers. Performed at about 400° C.
8. Spin-On Glass (SOG) Coat/Cure and Etch Back. An inorganic material is spun onto the substrate to planarize the PECVD oxide, and then treated at 400-450° C. to form inorganic oxide. The wafer is plasma etched with a 1:1 ratio to smooth the edges of the PECVD oxide covering the M
1
layer.
9. PECVD Oxide Deposition II. A second layer of PECVD oxide is deposited (at about 400° C.) to thicken the interlayer dielectric provided by the PECVD Oxide Deposition I and the SOG coat/cure steps.
10. Via Mask. A via mask step opens holes in the interlayer dielectric to enable contact to the M
1
layer.
11. Sputter AlCu. This step, performed at about 400° C., creates the M
2
layer.
12. Metal
2
Mask. This step dry etches the AlCu according to the M
2
mask pattern.
13. Oxide/Oxynitride PECVD. Passivation is performed (at about 400° C.) using
2
layers: an undoped PECVD oxide layer followed by an oxynitride layer.
14. Seal Mask Oxynitride-oxide etch. The passivation layer is plasma etched in accordance with a seal mask to open holes to the M
2
bond pads.
15. Alloy. This step sinters and stabilizes the TF material; it is typically necessary to perform the alloying at a temperature of about 465° C. to stabilize the TF.
Unfortunately, the TF resistors fabricated with this process are adversely impacted by the high temperature process steps (e.g., AlCu sputter, SOG Coat/Cure, Alloy) which occur after the TF sputter step. Each high temperature step (>~375° C.) alters the TF characteristics. Since the thermal heat from a particular step is non-uniform and has a gradient, its effect on the TF material is also non-uniform. This results in sheet rho and thermal coefficient of resistivity (TCR) parameters which vary from one spot to another on an individual wafer, as well as from wafer to wafer. These adverse effects impact the accuracy of the resistance values, as well as how well the resistors can be matched. Furthermore, as the resistors are subjected to additional high temperature process steps, the magnitude of the variations increases.
SUMMARY OF THE INVENTION
A novel method for the stabilization of thin film structures fabricated on an I.C. substrate is presented, which avoids the problems noted above.
The stabilization method requires the performance of a rapid thermal annealing (RTA) step after the TF material, preferably silicon-chromium (SiCr) or silicon chromium carbide (SiCrC), is sputtered onto the wafer. The RTA step stabilizes the TF and thereby increases the integrity of the film. With the TF material stabilized, the effect of subsequent high temperature process steps on the film, and thus on structures formed with the TF, is reduced.
The novel stabilization method enables TF resistors thereby formed to attain a higher degree of accuracy, and thus to improve the ability with which such resistors can be matched. The consistency of resistor TCR and sheet rho is also improved, both within a given wafer, and from wafer to wafer. In addition, because the TF material is already stabilized via the RTA step, the temperature of the alloy process step (which was responsible for stabilizing the TF in the prior art process) can be reduced, which can improve device reliability.
Further features and advantages of the invention will be apparent to those skilled in the art from the following detailed description, taken together with the accompanying drawings.
REFERENCES:
patent: 6171922 (2001-01-01), Maghsoudnia
patent: 6211032 (2001-05-01), Redford et al.
Grebene, “Thin-Film Processes”,Bipolar and MOS Analog Integrated Circuit Design, John Wiley & Sons, Inc., pp. 22-26, (1984).
Hamilton et al, “Photolithography”,Basic Integrated Circuit Engineering, McGraw-Hill Book Company, pp. 8-12, (1975).
Sze, “Rapid Thermal Annealing”,VLSI Technology, Second Edition, McGraw-Hill Book Company, pp. 359-362, (1988).
Analog Devices Inc.
Kennedy Jennifer M.
Koppel & Jacobs
Niebling John F.
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