Hysterisis management for delay line

Details Hysterisis management for delay line Hysterisis management for delay line

2007-04-17

2007-04-17

Le, Dinh T. (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Having specific delay in producing output waveform

C327S261000

Reexamination Certificate

active

11147003

ABSTRACT:
A method and apparatus for managing hysterisis in a delay line. In one embodiment, an integrated circuit includes a delay line. A selection circuit is coupled to an input of the delay line. The selection circuit includes two inputs: a first input coupled to convey a signal such as a data signal or a data strobe signal, while the second input is coupled to convey a dummy clock signal. Control logic is coupled to monitor activity within the delay line. Upon detecting a lack of activity for a predetermined time period, the control logic is configured to cause the selection circuit to allow the dummy clock signal to be conveyed to the input of the delay line.

REFERENCES:
patent: 5402125 (1995-03-01), Distinti
patent: 5469476 (1995-11-01), Liao et al.
patent: 5867545 (1999-02-01), Ogasawara
patent: 6008680 (1999-12-01), Kyles et al.
patent: 6121815 (2000-09-01), Terada et al.

Affiliated with

Also associated with

Rating

Hysterisis management for delay line does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Hysterisis management for delay line, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Hysterisis management for delay line will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3799515