Hysteresis insensitive analog to digital converter system using

Details Hysteresis insensitive analog to digital converter system using Hysteresis insensitive analog to digital converter system using

1990-02-12

1991-04-09

Reinhart, Mark J.

Coded data generation or conversion

Analog to or from digital conversion

Analog to digital conversion

341167, 341172, H03M 112

Patent

active

050068539

ABSTRACT:
An analog to digital converter system (10) is disclosed which comprises an SAR logic circuit (12) which controls capacitor array control switches (14) which themselves control a capacitor array (16). A top plate (18) of the capacitor array (18) is selectively coupled to a coarse comparator (24) and a fine comparator (26). The outputs of the coarse comparator (24) and the fine comparator (26) are input into an error correction circuit (28). In operation, the coarse comparator (24) is used to approximate a predetermined number of the most significant bits of the digital word to be output by the system (10) while the fine comparator (26) is used to approximate the remaining bits of the digital word. In this manner, the coarse comparator (24) alone is subjected to the high voltages which might cause errors as a results of the hysteresis effect in the threshold voltages of the MOSFETs used to construct the comparators. The voltage shift as a result of this hysteresis is not a significant factor for the bits generated by the coarse comparator and as such the system (10) may accomplish high resolution analog to digital conversions.

REFERENCES:
patent: 3636555 (1972-01-01), Waaben
patent: 4380756 (1983-04-01), Worsman
patent: 4410879 (1983-10-01), Gumm et al.
patent: 4593271 (1986-06-01), Candy
patent: 4799042 (1989-01-01), Confalonieri et al.

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