Hysteresis comparator circuit

Details Hysteresis comparator circuit Hysteresis comparator circuit

1999-07-06

2001-01-09

Wells, Kenneth B. (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Specific signal discriminating without subsequent control

By amplitude

C327S206000, C327S205000, C360S046000, C360S051000

Reexamination Certificate

active

06172536

ABSTRACT:

FIELD OF THE INVENTION
This invention relates to a hysteresis comparator circuit, and more particularly to, a hysteresis comparator circuit that is composed of a differential input circuit and an adder circuit.
BACKGROUND OF THE INVENTION
A comparator circuit with a hysteresis characteristic is called a hysteresis comparator circuit, and is used for, e.g., a zero cross detection circuit. Such a zero cross detection circuit has been used as a delay detection circuit of receiving device.
In recent years, it is used as a modulator-demodulator circuit of mobile communication equipment, such as a portable telephone and PHS (personal handyphone system). In this use, required are such high sensitivity that can receive a weak signal and such low consumed power that can make the battery last a long time. An example of a hysteresis comparator circuit that complies with these requirements is disclosed in Japanese patent application laid-open No. 64-073906 (1989). This circuit is explained in detail below.
FIG. 1
shows the composition of the conventional hysteresis comparator circuit. Hereinafter, in transistors, PMOS means a p-type MOS (metal oxide semiconductor), and NMOS means n-type MOS.
The hysteresis comparator circuit is composed of input terminals
201
,
202
and
203
, a first differential input circuit
204
connected with these input terminals, an adder circuit
205
, a current switching circuit
206
, a PMOS transistor
207
, a NMOS transistor
208
with a gate connected with the input terminal
203
, a quantizer
209
and a NMOS transistor
210
.
The output end of the quantizer
209
is connected with an output terminal
211
. The NMOS transistor
210
has a gate connected with the input terminal
203
and a drain connected with the low-potential side of the current switching circuit
206
. The adder circuit
205
is disposed between the first differential input circuit
204
and a high-potential power source
212
. The gate of the PMOS transistor
207
is connected with output point B of the adder circuit
205
. The input end of the quantizer
209
is the drains of the PMOS transistor
207
and the NMOS transistor
208
.
The first differential input circuit
204
is composed of a NMOS transistor
204
a
with a gate connected with the input terminal
202
, a NMOS transistor
204
b
with a gate connected with the input terminal
201
, and a NMOS transistor
204
c
with a gate connected with the input terminal
203
. The drain of the NMOS transistor
204
c
is connected with the sources of the NMOS transistor
204
a
,
204
b
. The adder circuit
205
is composed of PMOS transistors
205
a,
205
b
that have gates connected commonly and have drains connected with the drains of the NMOS transistors
204
a
,
204
b
, respectively.
The current switching circuit
206
is composed of NMOS transistors
206
a
,
206
b.
The gate of the NMOS transistor
206
a
is connected with the output of the quantizer
209
and the output terminal
211
. The sources of the NMOS transistors
206
a
,
206
b
are connected each other, and the drains thereof are connected with the drains of the PMOS transistors
205
a
,
205
b
. Further, the sources of the NMOS transistors
206
a
,
206
b
are connected with the drain of the NMOS transistor
210
. The quantizer
209
is composed of two inverters
209
a
,
209
b
connected in series, and generates an output signal when a signal of higher than a certain level is input. The NMOS transistor
210
operates as a constant current source.
FIG. 2
shows operation waveforms of the hysteresis comparator circuit in FIG.
1
. The first differential input circuit
204
and the adder circuit
205
form a comparator. As shown in
FIG. 2
(
a
), reference voltage (V
REF
) is applied to the input terminal
201
, input voltage V
IN
is applied to the input terminal
202
, constant voltage (bias voltage) is applied to the input terminal
203
, the NMOS transistors
204
c
,
208
and
210
each function as a constant current source. Here, when voltages at output points m, n of the adder circuit
205
are equal, i.e., when I
1
and I
2
to flow through the PMOS transistors
205
a
,
205
b
, respectively are equal, is the threshold value of comparator.
When as shown in
FIG. 2
(
a
) the relation of V
REF
>V
IN
is given, drain currents I
a
, I
b
flow through the NMOS transistors
204
a
,
204
b
as shown in
FIG. 2
(
d
). In this gate, since the PMOS transistor
207
turns on and the input of the quantizer
209
is at H level, the output terminal
211
outputs output voltage V
211
of H level as shown in
FIG. 2
(
a
). Since the NMOS transistor
206
a
turns on inputting voltage V
211
of the output terminal
211
, drain current I
o
(=drain current &agr; of the NMOS transistor
210
) flows through the NMOS transistor
206
a
but does not flow through
206
b.
Then, as shown in
FIG. 2
(
a
), when V
IN
increases gradually and the relation of V
IN
>V
REF
occurs at time point t
1
, drain current I
c
of the NMOS transistor
204
a
tends to increase and drain current I
d
of the NMOS transistor
204
b
tends to reduce. With this change, drain current I
b
of the PMOS transistor
205
b
starts reducing and the potential of point n starts lowering gradually. When it lowers to a certain value, voltage that the inverter
209
a
can start operating is input to the inverter
209
a
. This time point is t
2
, when the output of the inverter
209
a
turns into H level and the output of the inverter
209
b
turns into L level. Therefore, as shown in
FIG. 2
(
b
), the NMOS transistor
206
b
turns into ON state, and at the same time, as shown in
FIG. 2
(
c
), the NMOS transistor turns into OFF state. This time point (t
2
) when the output change occurs is later than time point t
1
when V
IN
>V
REF
occurs. Namely, a hysteresis characteristic is obtained. Hereupon, as shown in
FIG. 2
(
d
), current I
a
, i.e., the sum of (drain current I
c
of the NMOS transistor
204
a
−drain current I
f
of the NMOS transistor
206
b
), flows through the PMOS transistor
205
a
of the adder circuit
205
, and drain current I
b
of the PMOS transistor
205
b
reduces. Also, as shown in
FIG. 2
(
e
), drain current &agr; of the NMOS transistor
210
increases in response to the switching of NMOS transistors
204
a
and
204
b.
Then, after the output terminal
211
becomes L level, as V
IN
starts reducing gradually, drain current I
d
of the NMOS transistor
204
b
starts increasing responsively and, on the contrary, drain current I
c
of the NMOS transistor
204
a
starts reducing. Then, at time point t
3
, it turns into V
REF
>V
IN
. However, at time point t
3
, since the drain output of the PMOS transistor
207
does not increase up to such voltage that can make the quantizer
209
and the current switching circuit
206
operate, the inverter
209
a
does not come to operation. At time point t
4
a little later than the time point when turned into V
REF
>V
IN
, the input of the inverter
209
a
reaches H level, when the output of the inverter
209
a
turns into L level and the output of the inverter
209
b
turns into H level. Namely, the voltage level of the output terminal
211
turns from L level into H level. That this time point t
4
is later than time point t
3
shows a hysteresis characteristic is provided.
Thus, the comparator circuit in
FIG. 1
conducts the hysteresis operation that when the start turns into V
IN
>V
REF
or V
REF
>V
IN
, the voltage level of the output terminal
211
changes delaying.
However, in the conventional hysteresis comparator circuit, when the output level of the quantizer
209
is high, the NMOS transistors
206
a
,
206
b
of the current switching circuit
206
exceed the linear region as a differential amplifier and as shown in
FIGS. 2
(
b
), (
c
), operate as a switch to switch current. Therefore, the matching effect of transfer characteristic as a differential amplifier does not occur, and the hysteresis width is determined by drain current of the NMOS transistor
210
and the mutual conductance of the NMOS tr

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