Hypersystolic Reed-Solomon decoder

Details Hypersystolic Reed-Solomon decoder Hypersystolic Reed-Solomon decoder

1988-11-21

1990-09-18

Smith, Jerry

Excavating

371 42, G06F 1110

Patent

active

049583484

ABSTRACT:
A Reed-Solomon decoder is implemented in systolic arrays wherein clock and control information propagate serially with the data. Progressive loss of coherence in such arrays is compensated by a folded array structure symmetrized in clock control whereby coherence is progressively re-established at the output of each such array.

REFERENCES:
patent: 4665523 (1987-05-01), Citron et al.
Kung, S. et al., "Wavefront Array Processor . . . ", IEEE Trans on Computers, vol. C-31, No. 11(Nov. 1982), pp. 1054-1065.
"A Method for Solving Key Equation for Decoding Goppa Codes" by Yasuo Sugiyama, Masao Kasahara, Shigeichi Hiraswa, and Toshihiko Hamekawa, Information and Control 27, 87-89 (1975), pp. 87-99.
"Systolic Stacks, Queues, and Counters" by Leo J. Guibas and Frank M. Liang, 1982 Conference on Advanced Research In VSLI, M.I.T., Jan. 27, 1982 pp. 155-164.
"Design of the PSC:", A Programmable Systolic Chip: by Allan L. Fisher, H. T. Kung, Louis M. Monier, Hank Walker, and Yasunori Dohi, Proc. Third Caltech Conference on VLSI, Computer Sciences Press, 1983, pp. 287-302.
"Systolic VLSI Arrays for Polynomial GCD Computation", by Richard P. Brent and H. T. Kung, IEEE Transactions On Computers, vol. C-33, No. 8, Aug. 1984., pp. 731-736.

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