Hyperfrequency circuit comprising a dynamic divide-by-two freque

Electrical pulse counters – pulse dividers – or shift registers: c – Particular transfer means – Including logic circuit

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377121, 307279, H03K 2352, H03K 2700

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active

050035665

ABSTRACT:
A hyperfrequency dynamic divide-by-two frequency divider circuit includes an inverter stage A and a follower stage B, in which the output of the inverter stage is applied to the input of the follower stage via an interrupt transistor T.sub.1 which is controlled by the hyperfrequency input signal H having a frequency f.sub.e. The output Q of the follower stage B is fed back to the input of the inverter stage A and supplies the output signal having a frequency f=f.sub.e /2. The operation of the divider takes place subject to the conditions:

REFERENCES:
patent: 4025800 (1977-05-01), Wanlass
patent: 4114052 (1978-09-01), Manabe et al.
patent: 4250406 (1981-02-01), Alaspa
patent: 4450369 (1984-05-01), Schuermeyer
patent: 4707622 (1987-11-01), Takao et al.
M. Rocchi et al., "GaAs Digital Dynamic IC's for Applications up to 10 GHz", IEEE Journal of Solid-State Circuit, vol. SC-18, No. 3, Jun. 1983, pp. 369-376.
M. Rocchi et al., "GaAs Binary Frequency Dividers for High Speed Applications up to 10 GHz", Electronics Letters, vol. 17, No. 4, Feb. 19, 1981, pp. 168-169.

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