Hyper-concatenation across multiple parallel channels

Details Hyper-concatenation across multiple parallel channels Hyper-concatenation across multiple parallel channels

2006-06-20

2006-06-20

Vu, Huy D. (Department: 2665)

Multiplex communications

Communication techniques for information carried in plural...

Assembly or disassembly of messages having address headers

C370S381000, C370S419000, C370S503000

Reexamination Certificate

active

07065103

ABSTRACT:
A signal processor is adapted for aligning two or more hyper-concatenated data streams, each data stream being conveyed within a respective parallel channel and having substantially equivalent bit and frame rates. The signal processor comprises a respective channel processor for each channel for processing a respective data stream. Each channel processor includes a framer, a memory, an interface, and an output timer. The framer generates a local strobe signal indicative of a timing of incoming frames of the respective data stream. The memory buffers incoming bits of the respective data stream. The interface selectively sends the local strobe signal to, and receives a master strobe signal from, an adjacent channel processor. The output timer controls a timing of outgoing bits of the respective data stream based on a selected one of the local and master strobe signals.

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