Hybrid wafer scale microcircuit integration

Details Hybrid wafer scale microcircuit integration Hybrid wafer scale microcircuit integration

1990-04-13

1991-04-16

Chaudhuri, Olik

Fishing, trapping, and vermin destroying

437228, 437211, H01L 2156, H01L 2160, H01L 2182

Patent

active

050082132

ABSTRACT:
A wafer scale integration arrangement wherein integrated circuit die of varying size, fabrication processes, and function are commonly mounted in the same host wafer using a filled epoxy material of special characteristics. The mounting epoxy material also serves as a substrate for the die interconnecting conductors in regions adjacent the mounted die. The described assembly also includes a newly available photosensitive polyimide material as a planarization and passivation covering for the die and hose wafer and as a mounting surface for an interconnecting metal conductor array. Multiple levels of interconnection metal. Fabrication processes for the die to host wafer attachment and the passivation covering of the assembly are disclosed.

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