Hybrid transistor

Wave transmission lines and networks – Automatically controlled systems – With control of equalizer and/or delay network

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Details

357 51, 357 68, 357 81, 333247, H01L 2302, H01L 2702, H01L 2348

Patent

active

043933920

ABSTRACT:
A transistor package having input, reference (ground) and output terminals includes a ceramic base metallized to provide a ground plane and an isolated collector pad; and also includes a transistor die disposed on the pad. An equivalent output circuit of the transistor die describes an output impedance having a capacitive reactance. Pairs of wires are connected from the ground plane to the collector pad in series with DC blocking capacitors to provide an inductive reactance in parallel with the capacitive reactance of the transistor die. The pairs of wires are disposed in a transverse, preferably a substantially perpendicular, relationship and are connected to the collector pad at distributed, preferably uniformly distributed, positions along such area. This provides for a substantially uniform distribution of current throughout the transistor die and a substantially uniform junction temperature throughout the die. The value of the inductive reactance is chosen to resonate with the capacitive reactance of the transistor die at a frequency dependent upon the range of frequencies in which the transistor package will be operating. In this way, the output impedance of the transistor package is increased and the efficiency in the operation of the transistor package is enhanced.

REFERENCES:
patent: 3713006 (1973-01-01), Litty et al.
patent: 3886505 (1975-05-01), Jacobson
patent: 3969752 (1976-07-01), Martin et al.
patent: 4023198 (1977-05-01), Malone et al.
patent: 4213141 (1980-07-01), Colussi

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