Hybrid signature test method and apparatus

Details Hybrid signature test method and apparatus Hybrid signature test method and apparatus

1978-08-11

1980-08-05

Atkinson, Charles E.

Excavating

324 73R, G01R 3126, G06F 1100

Patent

active

042163749

ABSTRACT:
An apparatus and method for identifying faults in a digital logic circuit system combines the output of a feedback signature generator and a synchronous transition counter to provide a unique signature sensitive both to bit pattern timing and bit pattern sequence. A plurality of output signals of the circuit system produced in response to a preselected input signal pattern is processed synchronously through a feedback signature generator or feedback shift register network, such as a serial cyclic redundancy check (CRC) network, and a synchronous bit transition counting network. A preselected portion of the output of the bit transition counting network is combined with a preselected portion of the bits of the shift register network to obtain a pseudo-random characteristic output bit pattern, or signature, which is unique to the circuit system under test. The fault detecting capability approaches 100 percent with an imbedded indication of the input test pattern duration as verification.

REFERENCES:
patent: 3924181 (1975-12-01), Alderson
patent: 3976864 (1976-08-01), Gordon et al.
patent: 4059749 (1977-11-01), Feilchenfeld
patent: 4139147 (1979-02-01), Franke
Hayes, Generation of Optimal Transition Count Tests, IEEE Transactions _on Computers, vol. C-27, No. 1, Jan. 1978, pp. 36-41. _
Gordon and Nadig, Hexadecimal Signatures Identify Troublespots in _Microprocessor Systems, Electronics, Mar. 3, 1977, pp. 89-96. _

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