Hybrid semiconductor device implemented by combination of hetero

Details Hybrid semiconductor device implemented by combination of hetero Hybrid semiconductor device implemented by combination of hetero

1989-09-01

1991-04-30

Jackson, Jr., Jerome

Fishing, trapping, and vermin destroying

357 4, 357 34, 357 41, 357 16, 357 49, 437133, H01L 29205, H01L 2707

Patent

active

050123181

ABSTRACT:
A hybrid semiconductor device according to the present invention is implemented by an unipolar compound semiconductor transistor and a heterojunction bipolar transistor respectively formed in first and second multiple-level structures formed on a semi-insulating substrate, and the uppermost level of the first multiple-level structure is formed in a common layer which further provides the lowest level of the second multiple-level structure, wherein an isolation is given between the unipolar compound semiconductor transistor and the heterojunction bipolar transistor and penetrates from the common layer into the semi-insulating substrate, so that the first and second multiple-level structures are formed through a uniform epitaxial growth advantageous in the controllability.

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