Static information storage and retrieval – Floating gate – Multiple values
Reexamination Certificate
2011-06-14
2011-06-14
Ho, Hoai V (Department: 2827)
Static information storage and retrieval
Floating gate
Multiple values
C365S185280, C365S185180, C365S185190, C365S185240
Reexamination Certificate
active
07961511
ABSTRACT:
A hybrid method of programming a non-volatile memory cell to a final programmed state is described. The method described is a more robust protocol suitable for reliably programming selected memory cells while eliminating programming disturbs. The hybrid method comprises programming the non-volatile memory cell to a first state according to a first coarse programming mechanism, and programming the non-volatile memory cell according to a second different more precise programming mechanism thereby completing the programming of the non-volatile memory cell to the final programmed state. Additionally, the described method is particularly advantageous for programming multilevel chips.
REFERENCES:
patent: 5280446 (1994-01-01), Ma et al.
patent: 5406521 (1995-04-01), Hara
patent: 5521867 (1996-05-01), Chen et al.
patent: 5621684 (1997-04-01), Jung
patent: 5761121 (1998-06-01), Chang
patent: 5912842 (1999-06-01), Chang et al.
patent: 5966329 (1999-10-01), Hsu et al.
patent: 5969987 (1999-10-01), Blyth et al.
patent: 5973962 (1999-10-01), Kwon
patent: 6044015 (2000-03-01), Van Houdt et al.
patent: 6046935 (2000-04-01), Takeuchi et al.
patent: 6160737 (2000-12-01), Hsu et al.
patent: 6243290 (2001-06-01), Kurata et al.
patent: 6392931 (2002-05-01), Pasotti et al.
patent: 6529410 (2003-03-01), Han et al.
patent: 6657891 (2003-12-01), Shibata et al.
patent: 6807095 (2004-10-01), Chen et al.
patent: 6897522 (2005-05-01), Harari et al.
patent: 6975537 (2005-12-01), Lutze et al.
patent: 6992929 (2006-01-01), Chen et al.
patent: 6996003 (2006-02-01), Li et al.
patent: 7020017 (2006-03-01), Chen et al.
patent: 7035146 (2006-04-01), Hemink et al.
patent: 7042044 (2006-05-01), Wu
patent: 7057939 (2006-06-01), Li et al.
patent: 7110298 (2006-09-01), Moogat et al.
patent: 7151692 (2006-12-01), Wu
patent: 7230847 (2007-06-01), Samachisa
patent: 2002/0141240 (2002-10-01), Satoh et al.
patent: 2003/0109093 (2003-06-01), Harari et al.
patent: 2004/0170056 (2004-09-01), Shibata et al.
patent: 2004/0196695 (2004-10-01), Tanaka et al.
patent: 2005/0078527 (2005-04-01), Liu et al.
patent: 2005/0127428 (2005-06-01), Mokhlesi et al.
patent: 2005/0133860 (2005-06-01), Forbes
patent: 2005/0157552 (2005-07-01), Hemink et al.
patent: 2005/0162924 (2005-07-01), Guterman et al.
patent: 2005/0265063 (2005-12-01), Forbes
patent: 2007/0242514 (2007-10-01), Choi et al.
patent: 2007/0257307 (2007-11-01), Chen
Montanari, D.; Van Houdt, J; Wellekens D.; Vanhorebeek, G.; Haspeslagh, L.; Deferm, L.; Groeseneken, G.; Maes, H.E.; Multi-level charge storage in source-side injection flash EEPROM; Nonvolatile Memory Technology Conference, 1996., Sixth Biennial IEEE International; Jun. 24-26, 1996 pp. 80-83.
Jae-Duk Lee et al., “A New Programming Disturbance Phenomenon in NAND Flash Memory by Source/Drain Hot-Electrons Generated by GIDL Current,” Proceedings of IEEE 21stNon-Volatile Memory Semiconductor Workshop p31 (2006).
Yoocheol Shin et al., “A Novel NAND-type MONOS Memory using 63nm Process Technology for Multi-Gigabit Flash EEPROMs,” IEDM Tech. Digest p. 337 (2005).
Ken'ichiro Sonoda et al., “Compact Modeling of Source-Side Injection Programming for 90nm-Node AG-AND Flash Memory,” Int'l Conf. on Simulation of Semiconductor Processes and Devices, p. 123 (2005).
Dana Lee et al., “Vertical floating-gate 4.5F2Split-gate NOR Flash Memory at 110nm Node,” Digest of Technical Papers, 2004 Symposium on VLSI Technology (2004).
Cheng-Yuan Hsu et al., “Split-Gate NAND Flash Memory at 120nm Technology Node Featuring Fast Programming and Erase,” Digest of Technical Papers, 2004 Symposium on VLSI Technology (2004).
International Search Report dated Feb. 27, 2008 from corresponding International Application No. PCT/US2007/078774.
Written Opinion dated Feb. 27, 2008 from corresponding International Application No. PCT/US2007/078774.
Chen Changyuan
Dong Yingda
Lee Dana
Lutze Jeffrey
Daivis Wright Tremaine LLP
Ho Hoai V
Radke Jay
SanDisk Corporation
LandOfFree
Hybrid programming methods and systems for non-volatile... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Hybrid programming methods and systems for non-volatile..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Hybrid programming methods and systems for non-volatile... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2658073