Hybrid power MOSFET

Details Hybrid power MOSFET Hybrid power MOSFET

2001-07-23

2003-10-14

Cunningham, Terry D. (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Gating

Utilizing three or more electrode solid-state device

C327S427000, C327S434000

Reexamination Certificate

active

06633195

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to a hybrid power MOSFET having a MOSFET and a junction FET, the MOSFET and the junction FET being electrically connected in series.
BACKGROUND OF THE INVENTION
A hybrid power MOSFET is known from DE 196 10 135 C1. This known hybrid power MOSFET is described in detail with reference to FIG.
1
.
Referring to
FIG. 1
, this hybrid power MOSFET has a normally-off n-channel MOSFET
2
, in particular a low voltage power MOSFET, and a normally-on n-channel junction FET
4
. This high blocking-capability junction FET
4
is also referred to as a Junction Field Effect Transistor (JFET). These two FETs are electrically connected in series such that the source connection S of the junction FET
4
is electrically conductively connected to the drain connection D′ of the MOSFET
2
, and that the gate connection G of the junction FET
4
is electrically conductively connected to the source connection S′ of MOSFET
2
. This electrical interconnection of two semiconductor components is also called a cascode circuit, as is known. The low blocking-capability MOSFET
2
in this cascode circuit has an internal bipolar diode D
IN
which is connected in antiparallel with MOSFET
2
and is referred to generally as an inverse diode or internal freewheeling diode. The normally-off n-channel MOSFET
2
is made of silicon, whereas the normally-off n-channel JFET
4
is made of silicon carbide. This hybrid power MOSFET is designed for a high reverse voltage of over 600 volts and nevertheless has only low losses in the passband.
FIGS. 2
,
3
, and
4
show a few important characteristics for the normally-on junction FET
4
in more detail.
FIG. 2
shows various output characteristics for the junction FET
4
, whereas
FIG. 3
shows the transfer characteristic for the junction FET
4
. This transfer characteristic reveals that the largest drain current I
D
flows through the junction FET at a gate voltage U
G
=0. For this reason, such a junction FET
4
is referred to as normally on. If the gate voltage U
G
falls below a threshold voltage U
Th
, the drain current I
D
is equal to zero.
FIG. 4
shows the drain voltage U
DS
as a function of the gate voltage U
GS
for a constant drain current I
D
. The graph in
FIG. 2
reveals that a gate voltage U
GS
can be used to control the resistance between the drain connection D and the source connection S of the junction FET
4
. The control voltage is the gate voltage U
GS
. For this reason, a junction FET is also referred to as a controlled resistor.
This cascode circuit is controlled using the gate voltage U
G′S′
of the normally-off MOSFET
2
. If MOSFET
2
is on or the antiparallel internal diode D
IN
of MOSFET
2
is conducting a current, the drain voltage U
D′S′
of MOSFET
2
is approximately zero. The coupling between the gate connection of JFET
4
and the source connection S′ of MOSFET
2
means that the gate voltage U
GS′
of JFET
4
is zero to slightly negative or positive. In accordance with the transfer characteristic shown in
FIG. 3
, approximately the largest drain current I
D
flows through JFET
4
. If MOSFET
2
is turned off, the drain voltage UD
′S′
rises until the maximum permissible reverse voltage of MOSFET
2
has been reached. The value of the reverse voltage in a low voltage power MOSFET
2
is 30 volts, for example. As soon as the value of the drain voltage U
D′S′
of MOSFET
2
exceeds the value of the threshold voltage U
Th
, the drain current I
D
of JFET
4
is zero in accordance with the transfer characteristics shown in FIG.
3
. That is to say that the JFET
4
is off. The coupling between the gate connection G of JFET
4
and the source connection S′ of MOSFET
2
means that the drain voltage U
D′S′
of MOSFET
2
is fed back negatively to the gate G of JFET
4
.
The graph in
FIG. 5
shows the time profile for a turn-off operation in the hybrid power MOSFET from
FIG. 1
in more detail. The turn-off operation starts at the time t
1
. At this time t
1
, the drain voltage U
D′S′
of MOSFET
2
starts to rise, i.e. MOSFET
2
becomes live. As already mentioned, this voltage is fed back negatively to the gate G of JFET
4
in this case. Since the drain current I
D
does not change, but rather remains constant, the drain voltage U
DS′
of JFET
4
rises in accordance with the characteristic shown in FIG.
4
. As soon as this drain voltage U
DS′
of JFET
4
is equal to a DC voltage present on the hybrid power MOSFET (time t
3
), the drain current I
D
falls to the value zero in accordance with the transfer characteristic shown in FIG.
3
. This is the actual end of the turn-off operation. The continued increase in the drain voltage U
D′S′
of MOSFET
2
up to the time t
5
to its steady-state final value now only influences the blocking response of the hybrid power MOSFET.
MOSFETs are distinguished in that they switch very rapidly. The time interval t
1
to t
5
characterizing the turn-off operation is significantly shorter than 100 ns, in accordance with datasheet values. Additionally, in accordance with the characteristics in
FIGS. 3 and 4
, the switching edges of JFET
4
are complete within a span of a few volts, thus enormous gradients arise for voltage and current changes. Since a high value for a current change in connection with unavoidable leakage inductances results in high over-voltages on the component, and high voltage edges impair the EMC response (Electromagnetic Compatibility) of circuits and appliances, it is necessary to reduce these voltage and current change values.
SUMMARY OF THE INVENTION
The present invention provides a device for reducing the change in the gate voltage of the junction FET. Depending on the embodiment of this device, the change in the gate voltage of the JFET can be reduced directly or indirectly. Reducing the gate voltage change flattens the gradient of the voltage and current change, so that high over-voltages no longer arise on the hybrid power MOSFET.
In accordance with the present invention, the gate voltage change of the JFET is influenced directly by connecting a decoupling apparatus between the gate connection of the JFET and the source connection of the MOSFET of the hybrid power MOSFET. This decoupling apparatus is used to moderate or break up the hard coupling between the gate voltage of the JFET and the drain voltage of the MOSFET.
The simplest embodiment of a decoupling apparatus is a gate resistor. This gate resistor forms, together with the ever-present gate capacitance of the JFET, a time constant. The rapid change in the drain voltage of the MOSFET is slowed down by this timer which is formed, so that the switching gradient of the JFET is reduced. The time delay can be set on the basis of the gate capacitance provided for the JFET and on a predetermined gate resistance.
In one advantageous embodiment of the decoupling apparatus, a capacitor is electrically connected in parallel with the gate capacitance of the JFET of the hybrid power MOSFET. This capacitor and the gate resistor can be used to set the switching edge of the JFET of the hybrid power MOSFET virtually as desired.
In accordance with the present invention, the gate voltage change of the JFET is influenced indirectly by providing at least one control resistor linked to the gate connection of the MOSFET of the hybrid power MOSFET. This control resistor forms, together with a gate/drain capacitance provided for the MOSFET, a time constant for the MOSFET. Using this timer, the MOSFET turns off more slowly. In other words, the drain voltage of the MOSFET rises more slowly, as a result of which the JFET also turns off more slowly on account of the negative feedback of the drain voltage of the MOSFET to the gate of the JFET. So that as the change in the gate voltage of the JFET is reduced, the time delay of the MOSFET needs to be very large. This means that higher switching losses need to be accepted for the MOSFET.
In accordance

Affiliated with

Also associated with

Rating

Hybrid power MOSFET does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Hybrid power MOSFET, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Hybrid power MOSFET will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3146612