Miscellaneous active electrical nonlinear devices – circuits – and – Signal converting – shaping – or generating – Synchronizing
Reexamination Certificate
2002-12-17
2004-02-03
Le, Dinh T. (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Signal converting, shaping, or generating
Synchronizing
C327S156000, C331S025000
Reexamination Certificate
active
06686784
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention generally relates to a phase-locked loop (PLL) and, more particularly, to a hybrid phase-locked loop with digital processing and analog processing mixed therein.
2. Description of the Prior Art
FIG. 1
shows a conventional analog phase-locked loop. The analog phase-locked loop
10
includes frequency dividers
11
and
12
, a phase-frequency detector (PFD)
13
, a charge pump
14
, a loop filter
15
and a voltage-controlled oscillator (VCO)
16
. The phase-locked loop
10
divides an input reference signal F
ref
and an oscillation signal F
VCO
by the same/different multiple(s) such as M or/and N by using the frequency dividers
11
and
12
. Then, the phase-locked loop
10
evaluates the differences of phase and frequency between the output signals from the frequency dividers
11
and
12
by using the phase-frequency detector (PFD)
13
, so as to generate difference signals. The charge pump
14
and the loop filter
15
generate a control voltage V
C
according to the difference signals. The voltage-controlled oscillator
16
outputs an oscillation signal F
VCO
corresponding to the control voltage V
C
. The phase-locked loop
10
may change the frequency of the oscillation signal F
VCO
by varying the frequency-dividing multiple(s) of the frequency dividers
11
and
12
.
However, there exists a dilemma situation considering the circuit design. On the one hand, concerning the jitter of the reference signal F
ref
, the loop bandwidth F
LBW
of the PLL should be designed to be sufficiently narrow in order to filter out the F
ref
jitter; on the other hand, considering the jitter of the voltage-controlled oscillator
16
, the loop bandwidth of the PLL should be wide enough to eliminate the F
VCO
jitter. In addition to the dilemma situation in circuit design, there is also a problem related to the stabilization of the PLL. Generally, the PLL is reliable only when the ratio of F
LBW
of the PLL to the frequency of F
ref
satisfies the following inequality (1):
F
ref
F
LBW
≥
K
(
1
)
The inequality (1) comes into existence when the frequency of F
ref
is relatively high. However, when the frequency of F
ref
is low and the output frequency of the voltage-controlled oscillator is high, the jitter of the voltage-controlled oscillator cannot be effectively eliminated since the loop bandwidth F
LBW
of the PLL is not sufficiently large for the sake of stabilization. For example, in a liquid crystal display (LCD) controller chip, the frequency of the reference signal (i.e., the horizontal synchronous signal, HSYNC) F
ref
is in the range of 30 KHz~100 KHz and the frequency of the voltage-controlled oscillator is in the range of 25 MHz~200 MHz. The multiple is in the range of 800~2000. Therefore, the jitter of the voltage-controlled oscillator cannot be suppressed by using a conventional PLL.
SUMMARY OF THE INVENTION
In view of the aforementioned problems, it is the primary object of the present invention to provide a hybrid phase-locked loop with digital processing and analog processing mixed therein.
It is another object of the present invention to provide a hybrid phase-locked loop, in which the long-term jitter of a voltage-controlled oscillator is effectively reduced when the frequency of a reference signal is low and the jitter of the reference signal is large.
In order to achieve the foregoing objects, the present invention provides a hybrid phase-locked loop, comprising: a phase-frequency detector, for detecting the phase difference between a reference signal and an oscillation feedback signal and generating a digital phase-difference signal according to a mean-frequency signal; a digit pump, for receiving the phase-difference signal and generating a proportional gain signal and an accumulative gain signal according to a proportional gain value and an accumulative gain value; a digital filter, for receiving the proportional gain signal and the accumulative gain signal so as to generate a digital control signal; a digital-controlled oscillator (DCO), for receiving the control signal and the mean-frequency signal so as to generate a phase-swap signal; a phase selector, for receiving a plurality of multi-phase signals and the phase-swap signal so as to select one among neighboring phases to be the mean-frequency signal according to the phase-swap signal; an analog phase-locked loop, for receiving the mean-frequency signal and filtering out the cycle-to-cycle jitter thereof so as to generate an output signal; and a frequency divider, for receiving the output signal and dividing the frequency thereof so as to generate an oscillation feedback signal.
Other and further features, advantages and benefits of the invention will become apparent in the following description taken in conjunction with the following drawings. It is to be understood that the foregoing general description and following detailed description are exemplary and explanatory but are not to be restrictive of the invention. The accompanying drawings are incorporated in and constitute a part of this application and, together with the description, serve to explain the principles of the invention in general terms.
REFERENCES:
patent: 6028488 (2000-02-01), Landman et al.
patent: 6052034 (2000-04-01), Wang et al.
Le Dinh T.
Realtek Semiconductor Corp.
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