Hybrid phase/delay locked loop circuits and methods

Details Hybrid phase/delay locked loop circuits and methods Hybrid phase/delay locked loop circuits and methods

2006-02-07

2006-02-07

Callahan, Timothy P. (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Synchronizing

C327S159000, C327S263000

Reexamination Certificate

active

06995590

ABSTRACT:
A circuit is provided that aligns the phase of a delay signal with an input clock signal. The circuit functions as a phase locked loop (PLL) in a first state of operation and as a delay locked loop (DLL) in a second state of operation. An adjustable delay circuit generates the delay signal. A phase detector compares the input clock signal to the delay signal to generate a phase detection signal. The adjustable delay circuit adjusts the phase of the delay signal in response to the phase detection signal. A multiplexer couples the delay signal back to the input of the adjustable delay circuit using a feedback loop in the first state of operation. The multiplexer couples the input clock signal to the input of the adjustable delay circuit in the second state of operation.

REFERENCES:
patent: 5150863 (1992-09-01), Hozumi
patent: 5506878 (1996-04-01), Chiang
patent: 5771264 (1998-06-01), Lane
patent: 5815016 (1998-09-01), Erickson
patent: 5999025 (1999-12-01), New
patent: 6114915 (2000-09-01), Huang et al.
patent: 6150863 (2000-11-01), Conn et al.
patent: 6191613 (2001-02-01), Schultz et al.
patent: 6204695 (2001-03-01), Alfke et al.
patent: 6252419 (2001-06-01), Sung et al.
patent: 6271729 (2001-08-01), Sung et al.
patent: 6282253 (2001-08-01), Fahrenbruch
patent: 6292016 (2001-09-01), Jefferson et al.
patent: 6292116 (2001-09-01), Wang et al.
patent: 6326812 (2001-12-01), Jefferson
patent: 6777990 (2004-08-01), Partsch et al.

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