1996-12-02
1997-11-25
Canney, Vincent P.
Excavating
39518603, G06F 1100
Patent
active
056919905
ABSTRACT:
An efficient method of selecting flip-flops to be made scannable in a digital integrated circuit design for purposes of improving testability without incurring the overhead of full-scan, comprising the steps of (a) partitioning the faults in the circuit into a first fault type and a second fault type, (b) selecting a static characterization algorithm for characterizing the first and second fault types, (c) determining the relationship between attainable fault coverage and the characterized values for the first and second fault types, (d) characterizing the first and second fault types for each candidate flip-flop for scan in the digital integrated circuit with the static characterization algorithm, (e) determining the first and second fault types that are the closest together in value, (f) selecting the flip-flop associated with the first and second fault types determined in step (e), (g) forming a shift register with flip-flop selected in step (f), (h) repeating steps (d)-(g) until the attainable fault coverage determined in step (c) is attained, and (i) generating test data for the network with the shift register configured in step (h).
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Partial Scan Flip-Flop Selection by Use of Empirical Testability, Journal of Electronic Testing: Theory and Application, 7, 47-49 (1995).
Kapur Rohit
Snethen Thomas J.
Zarrineh Kamran K.
Canney Vincent P.
International Business Machines - Corporation
Peterson Peter W.
Schnurmann H. Daniel
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