Semiconductor device manufacturing: process – With measuring or testing
Reexamination Certificate
2000-04-14
2001-10-09
Everhart, Caridad (Department: 2825)
Semiconductor device manufacturing: process
With measuring or testing
C438S015000, C438S017000, C438S018000, C438S005000, C438S003000
Reexamination Certificate
active
06300146
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to semiconductor devices and, more specifically relates to a semiconductor device in which an integrated temperature sensing and control die is mounted in the same housing as a MOS gated power semiconductor device.
The determination of the temperature of a MOS gate controlled semiconductor device, under transient as well as under steady state conditions, is highly desirable to attain high levels of operational reliability of the device. As an example, the device may be shut down at a predetermined die temperature. Also, overcurrent protection can be attained as a function of the die temperature and time.
Though control and protection circuits may be integrated into the same monolithic chip as the power device to enable direct temperature measurement of the power device, such monolithic devices are complex and complicate the manufacturing process of the discrete simpler power devices. Furthermore, there is less flexibility in the choice of control functions that can be integrated with the power device.
It is therefore desirable to co-package a discrete power semiconductor device with a separate die that includes the control and protection functions. By separating the control and protection functions from the power device, however, the temperature sensing circuitry is mounted at a distance away from the power device or is mounted with the power device on a common substrate that has a relatively high thermal resistance. This separation or thermal resistance prevents the temperature sensing circuitry from readily determining the temperature of the power device junctions. Moreover, the separation and thermal resistance hinder the determination of temperature under transient conditions.
It is therefore desirable that temperature sensing elements in the control die have the capability of accurately and dynamically determining the temperature of the power device.
SUMMARY OF THE INVENTION
The present invention provides a power semiconductor device that is co-packaged with a control and temperature sensing (or logic) die which is integrated into a small power die which is smaller than the main power die but which has a thermal response that is the same or similar to that of the power device. The smaller power device heats the logic elements by an amount proportional to the heating of the main power device. Temperature sensors are included in the smaller die to measure the temperature of the smaller device as well as that of the substrate which carries both the main and smaller die, providing signals to the logic circuits in the smaller die.
In carrying out the invention, the semiconductor devices may be copacked in a common device package that is comprised of a conductive lead frame which has a main pad area and has pins that are separated from each other. The main pad area is electrically coupled to at least one of the pins. A molded housing encapsulates the lead frame, and the pins extend beyond an external boundary of the molded housing and are available for external connection. First and second semiconductor die have opposing surfaces which contain respective electrodes are mounted on the main pad. The first semiconductor die consists of a first semiconductor device such as a standard discrete power MOSFET or other MOS gated power device. The second semiconductor die comprises a second semiconductor device which also may be a power MOSFET or other MOS gated power device which has temperature sensors and logic circuits integrated therein and is much smaller than the first device. A first thermal sensor is arranged on the second die adjacent to the second semiconductor device, and a second thermal sensor is arranged on the second die distant from the second semiconductor device. One of the opposing surfaces of each of the first and second semiconductor die are disposed atop and are in thermal contact with the main pad area. At least the first die is also in electrical contract with the main pad area. The first and second die are laterally spaced from each other. The opposite surfaces of the first and second die are electrically connected to respective pins as well as to each other such that the semiconductor devices are connected in parallel.
In accordance with this embodiment, the smaller MOSFET serves as a temperature sensing MOSFET and is connected in parallel to the main power MOSFET. A first thermal sensor is arranged either within or in close proximity to the sensing MOSFET to determine the temperature of the sensing MOSFET. A second temperature sensor is arranged on the control and temperature sensing die at a remote position with respect to the temperature sensing MOSFET cells so that the temperature of the lead frame can be measured. The ratio of the power dissipated by the temperature sensing MOSFET to that of the power MOSFET is known, and from this ratio and the measured temperatures, the temperature of the power MOSFET is determined.
The temperature sensors may be comprised of multiple identical sensor elements, such as series-connected polysilicon diodes, to simplify the determination of the measured value.
In accordance with another aspect of the invention, the temperature of the first semiconductor device of the package is determined from the temperature values measured by the first and second thermal sensors.
The novel invention is a form of a new “thermal mirror” circuit which is copacked with a standard discrete power MOSFET chip.
Thus, a logic chip, which can be made with a 10 mask process controls a 4 mask discrete chip which may be of the type shown in U.S. Pat. No. 5,795,793. The problem solved arises because the logic chip and discrete FET have a different R
DSON
×area (for example, 200 m&OHgr;mm
2
for the logic chip and 100 m&OHgr;mm
2
for the discrete FET). A basic concept of the invention is to produce an output signal related to the main FET temperature (T
FET
) of the following form:
T
FET
≈(
K+
0.2)(
T
SENSE
−T
TAB
)+
T
TAB
where
K=a technology factor (the ratio of R
DSON
×area of the 2 different technologies). The added 0.2 factor adjusts for lateral temperature differences in the logic die. In the example given K is 2.0.
T
SENSE
=temperature produced by a small MOSFET in the logic die, generating the logic die temperature.
T
TAB
=the temperature of the common support of the two die.
Once T
FET
reaches 150° C. (or some other predetermined temperature), the FET is turned off.
Other features and advantages of the invention will become apparent from the following description of the invention which refers to the accompanying drawings.
REFERENCES:
patent: 5851846 (1998-12-01), Matsui et al.
patent: 5886397 (1999-03-01), Ewer
patent: 6078098 (2000-06-01), Ewer
patent: 6184585 (2001-02-01), Martinez et al.
patent: 6204554 (2001-03-01), Ewer
Everhart Caridad
International Rectifier Corp.
Ostrolenk Faber Gerb & Soffen, LLP
Yevsikov V.
LandOfFree
Hybrid package including a power MOSFET die and a control... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Hybrid package including a power MOSFET die and a control..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Hybrid package including a power MOSFET die and a control... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2611803