Hybrid multipliers implemented using DSP circuitry and...

Details Hybrid multipliers implemented using DSP circuitry and... Hybrid multipliers implemented using DSP circuitry and...

2007-09-11

2007-09-11

Malzahn, D. H. (Department: 2193)

Electrical computers: arithmetic processing and calculating

Electrical digital calculating computer

Particular function performed

Reexamination Certificate

active

10712500

ABSTRACT:
A user logic design to hardware application is provided that efficiently implements in a PLD a user logic design multiplier using both programmable logic circuitry and one or more multipliers embedded in DSP circuitry integrated in the PLD. A smaller DSP multiplier may be used by implementing the user logic design multiplier in a sum of partial product arrangement in which one of the partial products is generated using the smaller DSP multiplier with the remaining partial products being generated by multipliers implemented using programmable logic circuitry.

REFERENCES:
patent: 6483343 (2002-11-01), Faith et al.
patent: 6943579 (2005-09-01), Hazanchuk et al.
patent: 7119576 (2006-10-01), Langhammer et al.
patent: 7142010 (2006-11-01), Langhammer et al.

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