Coded data generation or conversion – Analog to or from digital conversion – Differential encoder and/or decoder
Reexamination Certificate
2001-01-31
2003-08-19
Jeanglaude, Jean Bruner (Department: 2819)
Coded data generation or conversion
Analog to or from digital conversion
Differential encoder and/or decoder
C341S155000
Reexamination Certificate
active
06608575
ABSTRACT:
BACKGROUND OF THE INVENTION
I. Field of the Invention
The present invention relates to circuits. More particularly, the present invention relates to a hybrid multi-sampling circuit utilizing different types of sampling circuit.
II. Description of the Related Art
Many communication and data transmission systems employ active filters, analog-to-digital converters (ADCs), and other active circuits to perform some of the required signal processing. These active circuits may utilize operational amplifiers (op-amps) as one of the basic building elements. The amplifiers can be designed to provide high input impedance and large signal gain.
When implemented in an integrated circuit, an amplifier inherently exhibits some amount of DC offset and low frequency (1/f) noise at its input. These effects are worse when a low-voltage CMOS process is used to fabricate the amplifier. Also, the achievable amplifier gain is typically low in such process technology, relative to other linear-IC processes such as bipolar.
The input DC offset, low frequency noise, and low gain of an amplifier can contribute to degrade the performance of an active circuit that employ such amplifier. For a filter or ADC, such performance degradation may correspond to a reduced dynamic range, which may translate into worse overall performance for the system that employs the filter or ADC.
Many active filters and ADCs fabricated within CMOS integrated circuits are designed and implemented using switched capacitor circuits. Switched capacitor circuits employ amplifiers, capacitors, and switches, all of which can be (relatively) easily fabricated in a CMOS process. It is well known that the power consumption of a CMOS circuit is related to its switching frequency (i.e., power consumption is proportional to f
S
). For many applications, such as cellular telephone, it is highly desirable to provide high performance at reduced power consumption. For lower power consumption, double-sampling and higher order sampling switched capacitor circuits can be designed and implemented. These “multi-sampling” switched capacitor circuits sample the signals at multiple (i.e., N) phases of a lower frequency clock (i.e., f
S
/N).
Multi-sampling switched capacitor circuits, while having lower power consumption and other advantages, are vulnerable to input DC offset and low frequency noise. Moreover, multi-sampling circuits are typically implemented with n signal paths, and these n-path circuits are sensitive to path mismatch which causes image error.
Thus, a circuit design that can provide some of the benefits of multi-sampling switched capacitor circuits while ameliorating the deleterious effects of input DC offset, low frequency noise, and path mismatch is highly desirable.
SUMMARY OF THE INVENTION
Certain aspects of the present invention provide a multi-stage circuit that utilizes different types of sampling circuit to combat the deleterious effects of input DC offset, low frequency noise, finite amplifier gain, and path mismatch while providing high performance and reduced power consumption. The multi-stage circuit includes a number of stages, with at least one stage being of a first type and at least one stage being of a second type.
Each stage of the first type receives either an input signal for the multi-stage circuit or an output signal from a preceding stage, processes (e.g., filters) the received signal, and provides a respective output signal. Each stage of the first type operates based on one or more clock signals having a frequency of f
S
(i.e., the sampling frequency). Each stage of the second type receives an output signal from a preceding stage, processes the received signal, and provides a respective output signal. Each stage of the second type operates based on a respective set of one or more clock signals having a divided frequency of f
S
/N
X
, where N
X
is a frequency scaling factor for that second type stage and is an integer greater than one.
Each stage of the first type may be implemented with a single-sampled circuit such as, for example, a correlated double-sampling (CDS) circuit, an auto-zeroing (AZ) circuit, a chopper stabilization (CS) circuit, or some other circuit capable of providing similar desired characteristics. Each stage of the second type may be implemented with a “multi-sampling” circuit, i.e., a double-sampling or higher order sampling circuit.
The multi-stage circuit may be designed to implement a (lowpass or bandpass) filter, a delta-sigma analog-to-digital converter (&Dgr;&Sgr; ADC), or some other circuit. Various responses and orders for the multi-stage circuit (e.g., filter or ADC) may be achieved by cascading the proper number of stages and selecting the proper transfer function for each stage.
The stages of the multi-stage circuit may be designed using sampled-data domain circuit techniques such as switched capacitor and switched current, or possibly continuous-time circuit techniques such as active-RC, gm-C, and MOSFET-C, or some other circuit technique. The multi-stage circuit may also be implemented in CMOS or some other IC process.
Various aspects, embodiments, and features of the invention are described in further detail below.
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patent: 4633223 (1986-12-01), Senderowicz
patent: 5648779 (1997-07-01), Cabler
patent: 5682161 (1997-10-01), Ribner et al.
patent: 5841822 (1998-11-01), Mittel et al.
patent: 5982315 (1999-11-01), Bazarjani et al.
patent: 6140950 (2000-10-01), Oprescu
patent: 6255974 (2001-07-01), Morizio et al.
Brown Charles D.
Pappas George C.
Qualcomm Incorporated
Wadsworth Philip R.
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