Hybrid MRAM array structure and operation

Details Hybrid MRAM array structure and operation Hybrid MRAM array structure and operation

2004-05-18

2010-06-08

Phung, Anh (Department: 2824)

Semiconductor device manufacturing: process

Having magnetic or ferroelectric component

C257S421000, C257SE21665, C257SE27006, C365S158000, C365S173000, C438S129000

Reexamination Certificate

active

07732221

ABSTRACT:
This invention relates to MRAM technology and new variations on MRAM array architecture to incorporate certain advantages from both cross-point and 1T-1MTJ architectures. The fast read-time and higher signal-to-noise ratio of the 1T-1MTJ architecture and the higher packing density of the cross-point architecture are both exploited by combining certain characteristics of these layouts. A single access transistor16is used to read the multiple MRAM cells in a segment of a column, which can be stacked vertically above one another in a plurality of MRAM array layers arranged in a “Z” axis direction.

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