Hybrid memory device and method for controlling same

Details Hybrid memory device and method for controlling same Hybrid memory device and method for controlling same

2000-05-02

2001-03-27

Elms, Richard (Department: 2824)

Static information storage and retrieval

Addressing

Particular decoder or driver circuit

C365S230010, C365S230080

Reexamination Certificate

active

06208581

ABSTRACT:

This application claims the benefit of Korean Patent Application No. 16768/1999, filed in Korea on May 11, 1999, which is hereby incorporated by reference.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a memory device, and more particularly, to a hybrid memory device using a static RAM cell and a plurality of ROM cells.
2. Description of the Related Art
FIG. 1
is a block diagram of a conventional hybrid memory device for driving a memory cell array
1
having a static RAM cell
11
and a ROM cell
12
. As shown in
FIG. 1
, a conventional hybrid memory device for driving the memory cell array
1
includes a static RAM control unit
2
for selecting the static RAM cell
11
in accordance with a write control signal /WE and a read control signal /RE; a static RAM decoder
3
for decoding an address ADD temporarily stored in a static RAM buffer
4
using a static RAM enable signal /CSSRAM; a static RAM data input/output unit
5
for storing data in the static RAM cell
11
in accordance with the static RAM enable signal /CSSRAM or for outputting the data stored in the static RAM cell
11
; a ROM control unit
6
selecting the ROM cell
12
in accordance with the read control signal /RE; a ROM decoder
7
for decoding an address ADD temporarily stored in a ROM buffer
8
in accordance with a ROM enable signal /CSROM; and a ROM data output unit
9
for outputting data stored in the ROM cell
12
. The operation of the conventional hybrid memory device will now be described with reference to
FIGS. 2A-2G
.
As shown in
FIGS. 2A-2G
, in the first interval (I) when the ROM enable signal /CSROM (
FIG. 2C
) is a high level and the static RAM enable signal /CSSRAM (
FIG. 2B
) is a low level, the address ADD temporarily stored in the static RAM buffer
4
is decoded by the static RAM decoder
3
. Using the decoded signal, the desired static RAM cell
11
of the memory cell array
1
is selected and enabled. Here, when the write control signal /WE (
FIG. 2D
) is a high level and the write control signal /RE (
FIG. 2E
) is a low level, the data stored in the selected static RAM cell
11
are externally outputted by the static RAM data input/output unit
5
. In contrast, when the write control signal /WE (
FIG. 2D
) and the read control signal /RE (
FIG. 2E
) are respectively low and high levels, the external data DIN, /DIN are stored in the static RAM cell
11
selected by the static RAM data input/output unit
5
.
In the second interval (II), both the static RAM enable signal /CSSRAM (
FIG. 2B
) and the ROM enable signal /CSROM (
FIG. 2C
) are high levels, and the hybrid device is in a stand-by mode. That is, an external dis-able state is set.
In the third interval (III), when the static RAM enable signal /CSSRAM (
FIG. 2B
) is a high level and the ROM enable signal /CSROM (
FIG. 2C
) is a low level, the address ADD stored in the ROM buffer
8
is decoded by the ROM decoder
7
. Thus, the desired ROM cell
12
of the hybrid memory cell array
1
is selected with respect to the decoded signal and enabled. Here, when the read control signal /RE is a low level, the data temporarily stored in the enabled ROM cell
12
are externally outputted by the ROM data output unit
9
.
However, the conventional hybrid memory device using the static RAM cell
11
and the ROM cell
12
has a problem in that the static RAM cell
11
and the ROM cell
12
respectively employ peripheral circuits such as the buffers
4
,
8
and the decoders
3
,
7
. As a result, the conventional hybrid memory device occupies an unnecessarily large layout area.
SUMMARY OF THE INVENTION
Accordingly, the present invention is directed to a hybrid memory device that substantially obviates one or more of the problems due to limitations and disadvantages of the related art.
An object of the present invention is to provide a hybrid memory device that improves the integration of a ROM cell wherein a static RAM cell and a ROM cell constitute a unit hybrid memory cell, thereby reducing a layout area because the static RAM cell and the ROM cell share a single peripheral circuit.
Additional features and advantages of the invention will be set forth in the description which follows, and in part will be apparent from the description, or may be learned by practice of the invention. The objectives and other advantages of the invention will be realized and attained by the structure particularly pointed out in the written description and claims hereof as well as the appended drawings.
To achieve these and other advantages and in accordance with the purpose of the present invention, as embodied and broadly described, a hybrid memory device using an array of hybrid memory cells with each hybrid memory cell having a static RAM cell and a plurality of ROM cells comprises a read/write control unit for controlling a reading/writing operation of a selected hybrid memory cell in accordance with a write control signal and a read control signal; a decoder for decoding an address temporarily stored in a buffer in accordance with a first enable signal and a second enable signal, the address including a column address and a row address; a column line selecting unit for selecting a column line of the hybrid memory cell array in accordance with the column address decoded by the decoder; a wordline driving unit for driving a wordline of the hybrid memory cell array in accordance with the row address decoded by the decoder; a static RAM data input/output unit for storing external data in the static RAM cell of the selected hybrid memory cell or externally outputting data stored in the static RAM cell of the selected hybrid memory cell; and a ROM data output unit for externally outputting data stored in a selected ROM cell among the plurality of ROM cells of the selected hybrid memory cell.
In another aspect, a method for controlling a hybrid memory device using an array of hybrid memory cells with each hybrid memory cell having a static RAM cell and a plurality of ROM cells comprises the steps of controlling a reading/writing operation of a selected hybrid memory cell in accordance with a write control signal and a read control signal; decoding an address temporarily stored in a buffer in accordance with a first enable signal and a second enable signal, the address including a column address and a row address; selecting a column line of the hybrid memory cell array in accordance with the decoded column address; driving a wordline of the hybrid memory cell array in accordance with the decoded row address; storing external data received via a static RAM data input/output unit in the static RAM cell of the selected hybrid memory cell; externally outputting data stored in the static RAM cell of the selected hybrid memory cell via a static RAM data input/output unit; and externally outputting data stored in a selected ROM cell among the plurality of ROM cells of the selected hybrid memory cell via a ROM data output unit.
It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory and are intended to provide further explanation of the invention as claimed.


REFERENCES:
patent: 4972457 (1990-11-01), O'Sullivan
patent: 5757690 (1998-05-01), McMahon
patent: 6128218 (2000-10-01), You et al.
patent: 6134174 (2000-10-01), Takase

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