Hybrid low-pass sigma-delta modulator

Details Hybrid low-pass sigma-delta modulator Hybrid low-pass sigma-delta modulator

2001-03-06

2002-09-03

Williams, Howard L. (Department: 2819)

Coded data generation or conversion

Analog to or from digital conversion

Differential encoder and/or decoder

C341S172000, C327S554000, C333S173000

Reexamination Certificate

active

06445321

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to techniques for analog-to-digital (A/D) conversion. More particularly, the present invention relates to techniques for A/D conversion using a delta-sigma modulator.
2. The Prior Art
Many techniques are known in the prior art for A/D conversion. Each of these A/D techniques has advantages which correspond to the application in which the A/D conversion is being performed. Choosing the A/D conversion technique to be used in a particular application can depend on the consideration of at least the speed, accuracy, cost, dynamic range and power requirements of the application. The spectrum of A/D conversion techniques available in the prior art are commonly of two types.
In the first type of A/D technique, the analog input signal is directly compared to a digital reference value. The digital value output from the A/D conversion is equal to the digital reference value which most closely compares to the analog input signal. This category of A/D converters is considered fast, however, to obtain high resolution with A/D techniques in this category is generally expensive or quite difficult. In the second type of A/D technique, the analog input is converted into a quantity that is employed to represent a digital value corresponding to the analog input signal. This second type of A/D technique includes sigma-delta modulation.
A block diagram for an A/D modulator
10
employing a sigma-delta modulation technique is depicted in FIG.
1
. In the A/D modulator
10
, an analog input signal is oversampled and fed into a summing junction
12
that sums the analog input with a feedback signal formed as the output of the A/D modulator
10
. A common implementation of the summing junction
12
is a switched capacitor. By feeding back the output of the A/D modulator
10
into the summing junction
12
, the output of the summing junction
12
is kept at a zero average signal value. The output of the summing junction
12
, which represents the change in the value of the analog input signal from one sample to the next and which in summation represent a zero average signal value, is fed into an active loop filter
14
.
The output of the loop filter is fed into a comparator
16
for comparison with a reference value. When the output value is above the reference value, the output of the A/D modulator
10
is a high logic value, and a high logic value is fed back to the summing junction. When the integrated value is below the reference value, the output of the A/D modulator
10
is a low logic value, and a low logic value is fed back to the summing junction
12
. The high and low logic values formed as the bitstream output of the A/D modulator
10
are typically filtered at the output by a digital filter. The discussion of which is beyond the scope of this disclosure.
One of the major advantages associated with the sigma-delta modulation technique is that low resolution components can be used to process the analog input signal, and a high resolution digital output can be extracted because the A/D modulation does not depend on closely matched analog components.
Commonly the active loop filter
14
is implemented as either an active discrete-time loop filter or as a continuous-time loop filter. An example of an active discrete-time loop filter implemented as a simplified switched capacitor integrator
20
is depicted in FIG.
2
A. An example of a continuous-time loop filter implemented as a transconductance integrator
40
is illustrated in FIG.
2
B.
Turning now to
FIG. 2A
, the switched capacitor integrator
20
includes first and second switches
22
and
24
, commonly implemented with an MOS transistor, an input capacitor
26
, and operational amplifier
28
and a feedback capacitor
30
. An input to the switched capacitor integrator
20
may be coupled to input capacitor
26
by first switch
22
. A value stored on capacitor
26
can then be switched by second switch
24
to the input of an operational amplifier
28
. The feedback capacitor
30
is coupled in a feedback loop between the output of the operational amplifier
28
and the input of the operational amplifier
28
.
The performance by the switch capacitor integrator
20
to adequately provide high linearity and a fast settling time relies on the characteristics of the operational amplifier
28
. The requirements of high linearity and a fast settling time are typically satisfied with an operational amplifier
28
having a high bandwidth that is often greater by several orders than the bandwidth of the input signal, Vin, to the A/D modulator
10
. It will be appreciated by those of ordinary skill in the art, that the high bandwidth requirement of the operational amplifier
28
sets the lower boundary for the power consumption required by the A/D modulator
10
.
To reduce the power consumption required by the switch capacitor integrator
20
employed in an active discrete-time loop filter approach, the switched capacitor integrator
20
of
FIG. 2A
is replaced by the simplified transconductance-C integrator
40
of
FIG. 2B
in a continuous-time loop filter approach.
Turning to
FIG. 2B
, the transconductance integrator
40
includes an N-channel MOS transistor
42
having a source coupled to ground, a P-channel MOS transistor
44
having a source coupled to Vdd, an operational amplifier
46
and a feedback capacitor
48
. In the transconductance integrator
40
, an input signal representing the output of the summing junction
12
is coupled to the gate of N-channel MOS transistor
42
, and a bias voltage, Vb, is coupled to the gate of a P-channel MOS transistor
44
. The drains of N-channel MOS transistor
42
and P-channel MOS transistor
44
forming a common node are coupled to an input of the operational amplifier
46
. The feedback capacitor
48
is coupled in a feedback loop between the output of the operational amplifier
46
and the input of the operational amplifier
46
.
Although the power consumption of the continuous-time integrator of
FIG. 2B
is not as great as the power consumption of the discrete-time integrator of
FIG. 2A
, there are nonlinearities, even in a differential implementation (a single-ended implementation is depicted in FIG.
2
A), associated with the continuous-time integrator of
FIG. 2B
which are greater than the nonlinearities of the discrete-time integrator of FIG.
2
A. These nonlinearities increase the harmonic distortion and clock jitter sensitivity of the A/D modulator
10
, and degrade the dynamic range of the A/D modulator
10
by mixing the high-frequency quantization noise down to the baseband.
To avoid the problems associated with active loop filter designs typified by the active discrete-time loop filter in
FIG. 2A
, and the continuous-time loop filter approach of
FIG. 2B
, the loop filter
14
in the A/D modulator
10
has been implemented by a passive discrete-time loop filter as illustrated in FIG.
2
C. The passive discrete-time loop filter of
FIG. 2C
is implemented as a passive switched capacitor network
50
.
The passive switched capacitor network
50
includes input switches
52
,
54
, and
56
, a switched capacitor stage
58
having switches
60
,
62
,
64
, and
66
and capacitors
68
,
70
and
72
, and a phase margin stage
74
having switches
76
and
78
and capacitors
80
and
82
. The input switches
52
,
54
, and
56
are employed to couple the voltages Vin, Vref, and −Vref, respectively, to a first plate of capacitor
68
in the switched capacitor stage
58
. In the switched capacitor stage, the switches
60
and
62
are employed to couple a second plate of capacitor
68
to a ground (GND) reference potential and a first plate of capacitor
70
, respectively. The switch
64
is employed to couple the first plate of capacitor
70
to a first plate of capacitor
72
. The switch
66
is employed to couple the first plate of capacitor
72
to the comparator
16
. The second plates of capacitors
70
and
72
are connected to GND. In the phase margin stage
74
, switch
76
is employed

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