Boots – shoes – and leggings
Patent
1985-08-07
1988-09-27
Zache, Raulfe B.
Boots, shoes, and leggings
G06F 1206
Patent
active
047746530
ABSTRACT:
A hybrid hardware/software implementation of a translation look-aside buffer (TLB) is provided which improves the efficiency of address translation in a computing system utilizing a virtually addressed memory. To access a physical memory location a processor first attempts to fetch a virtual-to-physical address translation from a primary TLB. If the address translation is not in the primary TLB, the processor attempts to fetch the address translation from a secondary TLB. If the address translation is not in the secondary TLB, a trap is generated, after which the processor searches a virtual address translation table for the address translation. Through the use of the present invention, complex hashing routines can be used to address entries in a virtual address translation table (VATT) within the system's physical memory, without increasing the complexity or significantly reducing the performance of the TLB fetch hardware.
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Coleman Eric
Fromm Jeffery B.
Hewlett--Packard Company
Weller Douglas L.
Zache Raulfe B.
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