Hybrid fractional-bit systems

Details Hybrid fractional-bit systems Hybrid fractional-bit systems

2007-01-23

2007-01-23

Young, Brian (Department: 2819)

Coded data generation or conversion

Digital code to digital code converters

To or from multi-level codes

C341S057000

Reexamination Certificate

active

10907438

ABSTRACT:
The present invention abandons the conventional approach of incrementing bits-per-cell b by 1, but allows increments of states-per-cell N by as little as 1 between product generations. Because N is no longer an integral power of 2, b takes a fractional value, resulting in a fractional-bit system. In a fractional-bit system, cells are decoded in unit of word. By adjusting the word-width, the system efficiency can be optimized. Hybrid N-ary system can be used to improve manufacturing yield and endurance lifetime.

REFERENCES:
patent: 5103227 (1992-04-01), Betts
patent: 5498980 (1996-03-01), Bowles
patent: 5633631 (1997-05-01), Teckman
patent: 5659579 (1997-08-01), Herzberg
patent: 6040709 (2000-03-01), Kishimoto
patent: 6646913 (2003-11-01), Micheloni et al.
patent: 6717532 (2004-04-01), Noda
patent: 6816407 (2004-11-01), Rolandi
patent: 2005/0050434 (2005-03-01), Lunelli et al.
Tanaka et al. “A 3.4-Mbyte/sec Programming 3-Level NAND Flash Memory Saving 40% Die Size Per Bit”,1997 Symposium on VLSI Circuits Digest of Technical Papers, pp. 65-66 no month.
Micheloni et al. “The Flash Memory Read Path: Building Blocks and Critical Aspects”,Proceedings of the IEEE, pp. 537-551, Apr. 2003.

Affiliated with

Also associated with

Rating

Hybrid fractional-bit systems does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Hybrid fractional-bit systems, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Hybrid fractional-bit systems will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3782781