Hybrid extended drain concept for reduced hot electron effect

Details Hybrid extended drain concept for reduced hot electron effect Hybrid extended drain concept for reduced hot electron effect

1986-04-30

1987-09-08

Chaudhuri, Olik

Fishing, trapping, and vermin destroying

437 29, H01L 21425

Patent

active

046914331

ABSTRACT:
Hot electron injection into the gate oxides of MOSFET devices imposes limitations on the miniaturization of such devices in VLSI circuits. A buried channel with a surface spacer is provided to guard against hot electron trapping effects while preserving process and structure compatibility with micron or submicron VLSI devices. The channel current is redirected into a buried channel at a distance away from the interface in the vicinity of the drain region where the hot electron effect is most likely to occur. Additionally, a surface implant is performed to improve any gate control that may be lost as a result of the buried channel so as to mitigate any degradition of the current-voltage characteristics of the device.

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Mohler et al., IBM Tech. Disc. Bulletin, vol. 27, No. 7B (Dec., 1984), pp. 4362-4364.
Paul J. Tsang et al., "Fabrication of High-Performance LDDFET's with Oxide Sidewall-Spacer Technology", IEEE Journal of Solid-State Circuits, vol. SC-17, Apr. 1982, pp. 220-226.
Takeda et al., "Submicrometer MOSFET Structure for Minimizing Hot-Carrier Generation", IEEE Transactions on Electron Devices, vol. ED-29, No. 4, Apr. 1982.

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