Hybrid extended drain concept for reduced hot electron effect

Details Hybrid extended drain concept for reduced hot electron effect Hybrid extended drain concept for reduced hot electron effect

1985-04-12

1986-09-23

James, Andrew J.

357 2312, 357 238, 357 239, 357 90, 357 20, H01L 2978, H01L 2906

Patent

active

046138820

ABSTRACT:
Hot electron injection into the gate oxides of MOSFET devices imposes limitations on the miniaturization of such devices in VLSI circuits. A buried channel with a surface spacer is provided to guard against hot electron trapping effects while preserving process and structure compatibility with micron or submicron VLSI devices. The channel current is redirected into a buried channel at a distance away from the interface in the vicinity of the drain region where the hot electron effect is most likely to occur. Additionally, a surface implant is performed to improve any gate control that may be lost as a result of the buried channel so as to mitigate any degradation of the current-voltage characteristics of the device.

REFERENCES:
patent: 3936857 (1976-02-01), Ota
patent: 4247860 (1981-01-01), Tihanyi
patent: 4366613 (1983-01-01), Ogura et al.
Kiyoto Watabe, "LDD Structure Using Polysilicon on the Gate Sidewall", Presented at the 45th Japanese Applied Physics Conference, Oct. 12-15, 1984.
T. Wada, M. Nakamura, R. Dang and K. Taniguchi, "A Study of Hot-Carrier Degradation in Optimized 1 .mu.m LDD-MOSFET Using Device Simulator", Presented at the 45th Japanese Applied Physics Conference, Oct. 12-15, 1984.
"Tighter VLSI Geometries Create Problems with Hot Carriers" by Charles L. Cohen, Electronics, Jul. 15, 1985, pp. 36-37.

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